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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-07 22:13:10 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-27 10:39:20 +0000
commit56397364c9178cae527520a5fffb9eab2f6cc35b (patch)
tree6eef7e601f8e7c07c0e8f6f59caa776ade7af06f /src/superio/aspeed
parent46f04cbb49fbab5854d395edefea5b5f81df572e (diff)
binaryPI: Drop CAR teardown without POSTCAR_STAGE
The remaining (active) binaryPI boards moved away from BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now. As the cache_as_ram.S is also used with AGESA, this slightly reduces the codesize there for romstage and postcar as well. This commit is actually a revert for the vendorcode parts, AMD originally shipped the codes using 'invd' for the CAR teardown, but these were changed for coreboot due the convoluted teardown that used to happen with non-empty stack. Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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