superio: Add ASpeed AST2400

Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.

BUG = N/A
TEST = ASRock D1521D4U

Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

3 files changed, 122 insertions, 0 deletions

diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig
new file mode 100644
index 0000000000..3f0dabb853
--- /dev/null
+++ b/src/superio/aspeed/common/Kconfig
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+## Copyright (C) 2018 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# Generic Aspeed preram driver - Just enough UART initialisation code for
+# preram phase.
+config SUPERIO_ASPEED_COMMON_PRE_RAM
+	bool
+	default n
diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h
new file mode 100644
index 0000000000..d3774eab3e
--- /dev/null
+++ b/src/superio/aspeed/common/aspeed.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H
+#define SUPERIO_ASPEED_COMMON_ROMSTAGE_H
+
+#include <arch/io.h>
+#include <device/pnp_type.h>
+#include <stdint.h>
+
+void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase);
+
+void pnp_enter_conf_state(pnp_devfn_t dev);
+void pnp_exit_conf_state(pnp_devfn_t dev);
+
+#endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */
diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c
new file mode 100644
index 0000000000..7ac9474bcc
--- /dev/null
+++ b/src/superio/aspeed/common/early_serial.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * A generic pre-ram driver for Aspeed variant Super I/O chips.
+ *
+ * The following is derived directly from the vendor Aspeed's data-sheets:
+ *
+ * To toggle between `configuration mode` and `normal operation mode` as to
+ * manipulation the various LDN's in Aspeed Super I/O's we are required to
+ * pass magic numbers `passwords keys`.
+ *
+ *  ASPEED_ENTRY_KEY :=  enable  configuration : 0xA5 (twice!)
+ *  ASPEED_EXIT_KEY  :=  disable configuration : 0xAA
+ *
+ * To modify a LDN's configuration register, we use the index port to select
+ * the index of the LDN and then writing to the data port to alter the
+ * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a
+ * user modified pair is 0x2E, 0x2F respectively.
+ *
+ */
+
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <device/pnp_ops.h>
+#include <stdint.h>
+#include "aspeed.h"
+
+#define ASPEED_ENTRY_KEY 0xA5
+#define ASPEED_EXIT_KEY 0xAA
+
+/* Enable configuration: pass entry key '0xA5' into index port dev. */
+void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(ASPEED_ENTRY_KEY, port);
+	outb(ASPEED_ENTRY_KEY, port);
+}
+
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(ASPEED_EXIT_KEY, port);
+}
+
+/* Bring up early serial debugging output before the RAM is initialized. */
+void aspeed_enable_serial(pnp_devfn_t dev, u16 iobase)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}