superio/aspeed/ast2400: Add AST2500 support

The AST2500 is similar to the AST2400, but it also supports ESPI mode.
In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable.

Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 22 insertions, 0 deletions

diff --git a/src/superio/aspeed/ast2400/chip.h b/src/superio/aspeed/ast2400/chip.h
new file mode 100644
index 0000000000..4f1c5f022d
--- /dev/null
+++ b/src/superio/aspeed/ast2400/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SUPERIO_ASPEED__AST2400_CHIP_H__
+#define __SUPERIO_ASPEED__AST2400_CHIP_H__
+
+struct superio_aspeed_ast2400_config {
+	/* On AST2500 only 1: ESPI, 0: LPC */
+	bool use_espi;
+};
+
+#endif /* __SUPERIO_ASPEED__AST2400_CHIP_H__ */