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authorFelix Held <felix-coreboot@felixheld.de>2022-01-10 20:55:01 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-01-25 03:16:52 +0000
commit6abaccf13da19733720aa424d1bd125c84ba0d85 (patch)
tree83b2b3f96dba1cd08e05db8425bff88c05c19547 /src/superio/acpi
parentdd68649fe0e86837191ac6b8a75b1c26468f4a89 (diff)
vc/amd/fsp/sabrina: add as a copy of vc/amd/fsp/cezanne
The AMD Sabrina SoC will be using the FSP driver to call into the corresponding FSP binary to do its part of for the silicon initialization, so we need an initial set of FSP headers for the AMD Sabrina SoC code to build. Since the FSP interface for this SoC won't be too different from the Cezanne FSP interface, we'll start with a copy of the Cezanne FSP headers and update/replace them as soon as the proper FSP headers for Sabrina will be available. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib3bf50598efe60673b81cf99da491866fb5dc121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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