diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-13 23:26:44 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-30 01:17:53 +0000 |
| commit | 2b4d1480d6afe04cc4065f27abf6fc0c1fa8d9ae (patch) | |
| tree | 7050f26d1724b2b7fdc3e651f364f3908f1db29e /src/superio/acpi | |
| parent | c55012bd2ad6646c91c443fe70347b79fa371390 (diff) | |
mb/amd/chausie/port_descriptors: update DXIO descriptors
Change the DXIO descriptors to match the default PCIe lane mapping on
the chausie board. With this configuration and a board-level rework to
bypass the EC control of the NVMe SSD power supply rail, this
configuration results in the SSD being detected on the root port on bus
0 device 2 function 3 and usable as boot device. This was also validated
against the schematics revision B.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/acpi')
0 files changed, 0 insertions, 0 deletions