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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-10-12 10:38:39 -0600
committerMartin Roth <martinroth@google.com>2018-10-14 19:11:34 +0000
commitba8751fc722c4636d36331d0cf628d656d2b5cf4 (patch)
treecf53d7ed2054d5b03849008475cdd6cd1d28643e /src/superio/acpi/pnp_kbc.asl
parentc366f90a2e99828f28c39f9d715149cb14af4293 (diff)
soc/amd/stoneyridge: Rearrange southbridge.h more
Move the SPI base address register definition to D14F3. This was missed in: bba043 amd/stoneyridge: Rearrange southbridge.h Change-Id: Ia722339418c118bdf4b000bbf97ae4266e9b3be2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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