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authorSubrata Banik <subrata.banik@intel.com>2020-12-08 12:43:47 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-12-12 04:03:48 +0000
commit33cd957866ca8d8c7d86b7cfa50f926c40e8d540 (patch)
tree70039f4ce34196f1f12eab8f9b372aff641b40b0 /src/superio/Makefile.inc
parentf880eb061bf44101c65487bd74384a1ddcecce5e (diff)
mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable TEST=Able to detect PCIE SD card on 0x1 slot. Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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