sb/intel/ibexpeak: Drop Global NVS support

Was copy-pasted from bd82x6x and no mainboard actually needs it.

The few globals moved outside the GNVS will be removed, relocated or
replaced with acpigen later.

Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 0 insertions, 349 deletions

diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 18f77703a4..117827fa6e 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -8,7 +8,6 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK
 config SOUTH_BRIDGE_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ACPI_SOC_NVS
 	select AZALIA_PLUGIN_SUPPORT
 	select IOAPIC
 	select HAVE_SMI_HANDLER
diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
deleted file mode 100644
index cd37e283de..0000000000
--- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
+++ /dev/null
@@ -1,219 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Global Variables */
-
-Field (GNVS, ByteAcc, NoLock, Preserve)
-{
-	/* Miscellaneous */
-	,	16,	// 0x00 - Operating System
-	SMIF,	 8,	// 0x02 - SMI function
-	PRM0,	 8,	// 0x03 - SMI function parameter
-	PRM1,	 8,	// 0x04 - SMI function parameter
-	SCIF,	 8,	// 0x05 - SCI function
-	PRM2,	 8,	// 0x06 - SCI function parameter
-	PRM3,	 8,	// 0x07 - SCI function parameter
-	LCKF,	 8,	// 0x08 - Global Lock function for EC
-	PRM4,	 8,	// 0x09 - Lock function parameter
-	PRM5,	 8,	// 0x0a - Lock function parameter
-	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
-	LIDS,	 8,	// 0x0f - LID state (open = 1)
-	,	 8,	// 0x10 - Power State (AC = 1)
-	/* Thermal policy */
-	Offset (0x11),
-	TLVL,    8,	// 0x11 - Throttle Level Limit
-	FLVL,	 8,	// 0x12 - Current FAN Level
-	TCRT,    8,	// 0x13 - Critical Threshold
-	TPSV,	 8,	// 0x14 - Passive Threshold
-	TMAX,	 8,	// 0x15 - CPU Tj_max
-	F0OF,	 8,	// 0x16 - FAN 0 OFF Threshold
-	F0ON,	 8,	// 0x17 - FAN 0 ON Threshold
-	F0PW,	 8,	// 0x18 - FAN 0 PWM value
-	F1OF,	 8,	// 0x19 - FAN 1 OFF Threshold
-	F1ON,	 8,	// 0x1a - FAN 1 ON Threshold
-	F1PW,	 8,	// 0x1b - FAN 1 PWM value
-	F2OF,	 8,	// 0x1c - FAN 2 OFF Threshold
-	F2ON,	 8,	// 0x1d - FAN 2 ON Threshold
-	F2PW,	 8,	// 0x1e - FAN 2 PWM value
-	F3OF,	 8,	// 0x1f - FAN 3 OFF Threshold
-	F3ON,	 8,	// 0x20 - FAN 3 ON Threshold
-	F3PW,	 8,	// 0x21 - FAN 3 PWM value
-	F4OF,	 8,	// 0x22 - FAN 4 OFF Threshold
-	F4ON,	 8,	// 0x23 - FAN 4 ON Threshold
-	F4PW,	 8,	// 0x24 - FAN 4 PWM value
-	TMPS,    8,	// 0x25 - Temperature Sensor ID
-	/* Processor Identification */
-	Offset (0x28),
-	,	 8,	// 0x28 -  Enabled by coreboot
-	,	 8,	// 0x29 - Multi Processor Enable
-	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
-	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
-	PPCM,	 8,	// 0x2c - Max. PPC state
-	,	 8,	// 0x2d - Processor count
-	/* Super I/O & CMOS config */
-	Offset (0x32),
-	NATP,	 8,	// 0x32 -
-	S5U0,	 8,	// 0x33 - Enable USB0 in S5
-	S5U1,	 8,	// 0x34 - Enable USB1 in S5
-	S3U0,	 8,	// 0x35 - Enable USB0 in S3
-	S3U1,	 8,	// 0x36 - Enable USB1 in S3
-	S33G,	 8,	// 0x37 - Enable 3G in S3
-	,	 32,	// 0x38 - CBMEM TOC
-	/* Integrated Graphics Device */
-	Offset (0x3c),
-	IGDS,	 8,	// 0x3c - IGD state (primary = 1)
-	TLST,	 8,	// 0x3d - Display Toggle List pointer
-	CADL,	 8,	// 0x3e - Currently Attached Devices List
-	PADL,	 8,	// 0x3f - Previously Attached Devices List
-	/* Backlight Control */
-	Offset (0x64),
-	BLCS,	 8,	// 0x64 - Backlight control possible?
-	BRTL,	 8,	// 0x65 - Brightness Level
-	ODDS,	 8,	// 0x66
-	/* Ambient Light Sensors */
-	Offset (0x6e),
-	ALSE,	 8,	// 0x6e - ALS enable
-	ALAF,	 8,	// 0x6f - Ambient light adjustment factor
-	LLOW,	 8,	// 0x70 - LUX Low
-	LHIH,	 8,	// 0x71 - LUX High
-	/* EMA */
-	Offset (0x78),
-	EMAE,	 8,	// 0x78 - EMA enable
-	EMAP,	16,	// 0x79 - EMA pointer
-	EMAL,	16,	// 0x7b - EMA length
-	/* MEF */
-	Offset (0x82),
-	MEFE,	 8,	// 0x82 - MEF enable
-	/* TPM support */
-	Offset (0x8c),
-	TPMP,	 8,	// 0x8c - TPM
-	TPME,	 8,	// 0x8d - TPM enable
-	/* SATA */
-	Offset (0x96),
-	GTF0,	56,	// 0x96 - GTF task file buffer for port 0
-	GTF1,	56,	// 0x9d - GTF task file buffer for port 1
-	GTF2,	56,	// 0xa4 - GTF task file buffer for port 2
-	IDEM,	 8,	// 0xab - IDE mode (compatible / enhanced)
-	IDET,	 8,	// 0xac - IDE
-	/* XHCI */
-	Offset (0xb2),
-	XHCI,	 8,
-	CBMC,	32,
-	PM1I,	32,	// System Wake Source - PM1 Index
-	GPEI,	32,	// GPE Wake Source
-
-}
-
-/* Set flag to enable USB charging in S3 */
-Method (S3UE)
-{
-	Store (One, \S3U0)
-	Store (One, \S3U1)
-}
-
-/* Set flag to disable USB charging in S3 */
-Method (S3UD)
-{
-	Store (Zero, \S3U0)
-	Store (Zero, \S3U1)
-}
-
-/* Set flag to enable USB charging in S5 */
-Method (S5UE)
-{
-	Store (One, \S5U0)
-	Store (One, \S5U1)
-}
-
-/* Set flag to disable USB charging in S5 */
-Method (S5UD)
-{
-	Store (Zero, \S5U0)
-	Store (Zero, \S5U1)
-}
-
-/* Set flag to enable 3G module in S3 */
-Method (S3GE)
-{
-	Store (One, \S33G)
-}
-
-/* Set flag to disable 3G module in S3 */
-Method (S3GD)
-{
-	Store (Zero, \S33G)
-}
-
-/* Set XHCI Mode enable */
-Method (XHCE)
-{
-	Store (One, \XHCI)
-}
-
-/* Set XHCI Mode disable */
-Method (XHCD)
-{
-	Store (Zero, \XHCI)
-}
-External (\_TZ.SKIN)
-
-Method (TZUP)
-{
-#ifdef HAVE_THERMALZONE
-	/* Update Primary Thermal Zone */
-	If (CondRefOf (\_TZ.THRM)) {
-		Notify (\_TZ.THRM, 0x81)
-	}
-#endif
-
-	/* Update Secondary Thermal Zone */
-	If (CondRefOf (\_TZ.SKIN)) {
-		Notify (\_TZ.SKIN, 0x81)
-	}
-}
-
-/* Update Fan 0 thresholds */
-Method (F0UT, 2)
-{
-	Store (Arg0, \F0OF)
-	Store (Arg1, \F0ON)
-	TZUP ()
-}
-
-/* Update Fan 1 thresholds */
-Method (F1UT, 2)
-{
-	Store (Arg0, \F1OF)
-	Store (Arg1, \F1ON)
-	TZUP ()
-}
-
-/* Update Fan 2 thresholds */
-Method (F2UT, 2)
-{
-	Store (Arg0, \F2OF)
-	Store (Arg1, \F2ON)
-	TZUP ()
-}
-
-/* Update Fan 3 thresholds */
-Method (F3UT, 2)
-{
-	Store (Arg0, \F3OF)
-	Store (Arg1, \F3ON)
-	TZUP ()
-}
-
-/* Update Fan 4 thresholds */
-Method (F4UT, 2)
-{
-	Store (Arg0, \F4OF)
-	Store (Arg1, \F4ON)
-	TZUP ()
-}
-
-/* Update Temperature Sensor ID */
-Method (TMPU, 1)
-{
-	Store (Arg0, \TMPS)
-	TZUP ()
-}
diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
deleted file mode 100644
index 0676af27a0..0000000000
--- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H
-#define SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H
-
-#include <commonlib/helpers.h>
-#include <stdint.h>
-
-struct __packed global_nvs {
-	/* Miscellaneous */
-	u16	unused_was_osys; /* 0x00 - Operating System */
-	u8	smif; /* 0x02 - SMI function call ("TRAP") */
-	u8	prm0; /* 0x03 - SMI function call parameter */
-	u8	prm1; /* 0x04 - SMI function call parameter */
-	u8	scif; /* 0x05 - SCI function call (via _L00) */
-	u8	prm2; /* 0x06 - SCI function call parameter */
-	u8	prm3; /* 0x07 - SCI function call parameter */
-	u8	lckf; /* 0x08 - Global Lock function for EC */
-	u8	prm4; /* 0x09 - Lock function parameter */
-	u8	prm5; /* 0x0a - Lock function parameter */
-	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
-	u8	lids; /* 0x0f - LID state (open = 1) */
-	u8	unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
-	/* Thermal policy */
-	u8	tlvl; /* 0x11 - Throttle Level Limit */
-	u8	flvl; /* 0x12 - Current FAN Level */
-	u8	tcrt; /* 0x13 - Critical Threshold */
-	u8	tpsv; /* 0x14 - Passive Threshold */
-	u8	tmax; /* 0x15 - CPU Tj_max */
-	u8	f0of; /* 0x16 - FAN 0 OFF Threshold */
-	u8	f0on; /* 0x17 - FAN 0 ON Threshold */
-	u8	f0pw; /* 0x18 - FAN 0 PWM value */
-	u8	f1of; /* 0x19 - FAN 1 OFF Threshold */
-	u8	f1on; /* 0x1a - FAN 1 ON Threshold */
-	u8	f1pw; /* 0x1b - FAN 1 PWM value */
-	u8	f2of; /* 0x1c - FAN 2 OFF Threshold */
-	u8	f2on; /* 0x1d - FAN 2 ON Threshold */
-	u8	f2pw; /* 0x1e - FAN 2 PWM value */
-	u8	f3of; /* 0x1f - FAN 3 OFF Threshold */
-	u8	f3on; /* 0x20 - FAN 3 ON Threshold */
-	u8	f3pw; /* 0x21 - FAN 3 PWM value */
-	u8	f4of; /* 0x22 - FAN 4 OFF Threshold */
-	u8	f4on; /* 0x23 - FAN 4 ON Threshold */
-	u8	f4pw; /* 0x24 - FAN 4 PWM value */
-	u8	tmps; /* 0x25 - Temperature Sensor ID */
-	u8	rsvd3[2];
-	/* Processor Identification */
-	u8	unused_was_apic; /* 0x28 - APIC enabled */
-	u8	unused_was_mpen; /* 0x29 - MP capable/enabled */
-	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
-	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
-	u8	ppcm; /* 0x2c - Max. PPC state */
-	u8      unused_was_pcnt; /* 0x2d - Processor Count */
-	u8	rsvd4[4];
-	/* Super I/O & CMOS config */
-	u8	natp; /* 0x32 - SIO type */
-	u8	s5u0; /* 0x33 - Enable USB0 in S5 */
-	u8	s5u1; /* 0x34 - Enable USB1 in S5 */
-	u8	s3u0; /* 0x35 - Enable USB0 in S3 */
-	u8	s3u1; /* 0x36 - Enable USB1 in S3 */
-	u8	s33g; /* 0x37 - Enable S3 in 3G */
-	u32	obsolete_cmem; /* 0x38 - CBMEM TOC */
-	/* Integrated Graphics Device */
-	u8	igds; /* 0x3c - IGD state */
-	u8	tlst; /* 0x3d - Display Toggle List Pointer */
-	u8	cadl; /* 0x3e - currently attached devices */
-	u8	padl; /* 0x3f - previously attached devices */
-	u8	rsvd5[36];
-	/* Backlight Control */
-	u8	blcs; /* 0x64 - Backlight Control possible */
-	u8	brtl;
-	u8	odds;
-	u8	rsvd6[0x7];
-	/* Ambient Light Sensors*/
-	u8	alse; /* 0x6e - ALS enable */
-	u8	alaf;
-	u8	llow;
-	u8	lhih;
-	u8	rsvd7[0x6];
-	/* Extended Mobile Access */
-	u8	emae; /* 0x78 - EMA enable */
-	u16	emap; /* 0x79 - EMA pointer */
-	u16	emal; /* 0x7a - EMA Length */
-	u8	rsvd8[0x5];
-	/* MEF */
-	u8	mefe; /* 0x82 - MEF enable */
-	u8	rsvd9[0x9];
-	/* TPM support */
-	u8	tpmp; /* 0x8c - TPM */
-	u8	tpme;
-	u8	rsvd10[8];
-	/* SATA */
-	u8	gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
-	u8	gtf1[7];
-	u8	gtf2[7];
-	u8	idem;
-	u8	idet;
-	u8	rsvd11[6];
-	/* XHCI */
-	u8	xhci;
-
-	u32     cbmc;
-
-	/* Required for future unified acpi_save_wake_source. */
-	u32	pm1i;
-	u32	gpei;
-};
-
-#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index fe352777bc..5fb3077053 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -8,7 +8,6 @@
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
 #include <cpu/intel/model_2065x/model_2065x.h>
-#include <soc/nvs.h>
 #include <southbridge/intel/common/finalize.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/ibexpeak/me.h>
@@ -22,23 +21,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmutil.h>
 
-int southbridge_io_trap_handler(int smif)
-{
-	switch (smif) {
-	case 0x32:
-		printk(BIOS_DEBUG, "OS Init\n");
-		/* gnvs->smif:
-		 *  On success, the IO Trap Handler returns 0
-		 *  On failure, the IO Trap Handler returns a value != 0
-		 */
-		gnvs->smif = 0;
-		return 1; /* IO trap handled */
-	}
-
-	/* Not handled */
-	return 0;
-}
-
 static void southbridge_gate_memory_reset_real(int offset,
 					       u16 use, u16 io, u16 lvl)
 {
@@ -108,8 +90,6 @@ void southbridge_smi_monitor(void)
 
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
-		if (gnvs && gnvs->smif)
-			io_trap_handler(gnvs->smif); // call function smif
 		return;
 	}