diff options
| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-06-13 14:33:20 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:13:56 +0000 |
| commit | f69c96dd8d857a90143f1c2f38efd19e26b68039 (patch) | |
| tree | 70ae47a6645f1fafb7865e6b10b80ac5dc9c479a /src/southbridge | |
| parent | 493d36684c105d89372598bd4a937e97b2bdf05e (diff) | |
sb/amd/sr5650: Use 32 bit integers when disabling ports
This function attempts to set bits in the 20s of state and state_save,
which won't work since those variables are only 16 bits wide. Extend
them to 32 bits to capture all the bit operations.
Change-Id: I5616a2d879a85ff5f57af5af20384516659c62d6
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347384
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index f87fadbb08..6c42fdde4d 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -59,11 +59,11 @@ static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 { printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port); u32 reg; - u16 state_save; + u32 state_save; uint8_t i; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - u16 state = cfg->port_enable; + u32 state = cfg->port_enable; if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) state &= AtiPcieCfg.PortDetect; |