diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-23 13:23:40 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-23 13:23:40 +0000 |
commit | f0aa09b51b1874b8d52574d18a497162eda9cdf5 (patch) | |
tree | 3ea0d9eac449646489bb5f70b5c919664a4903fb /src/southbridge | |
parent | 0b2cda82b460098768d74dc4e01df00f78c60e41 (diff) |
fix newly introduced printk_foo warnings..
Interesting enough, console_printk was only used in a single place and
duplicated a large part of console.h which is included in the same place.
Thus, just drop console_printk.c and we're one down with console complexity
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/amd/rs780/rs780_gfx.c | 51 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx_lpc.c | 12 |
2 files changed, 31 insertions, 32 deletions
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index 2ec0683ebe..066dc60762 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -55,7 +55,7 @@ static u32 clkind_read(device_t dev, u32 index) static void clkind_write(device_t dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ + /* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; @@ -67,7 +67,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) */ static void rs780_gfx_read_resources(device_t dev) { - printk(BIOS_INFO, "rs780_gfx_read_resources.\n"); + printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n"); /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, @@ -307,7 +307,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", deviceid, vendorid); command = pci_read_config16(dev, 0x04); @@ -583,10 +583,10 @@ static void rs780_internal_gfx_enable(device_t dev) u32 FB_Start, FB_End; #endif - printk(BIOS_INFO, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); + printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); sysmem = rdmsr(0xc001001a); - printk(BIOS_INFO, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); + printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); /* The system top memory in 780. */ pci_write_config32(nb_dev, 0x90, sysmem.lo); @@ -824,12 +824,12 @@ static void single_port_configuration(device_t nb_dev, device_t dev) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n"); /* step 12 training, releases hold training for GFX port 0 (device 2) */ PcieReleasePortTraining(nb_dev, dev, 2); result = PcieTrainPort(nb_dev, dev, 2); - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step12.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n"); /* step 13 Power Down Control */ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ @@ -866,11 +866,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev) break; } } - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step13.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n"); /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step14.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n"); } static void dual_port_configuration(device_t nb_dev, device_t dev) @@ -980,7 +980,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk(BIOS_INFO, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", + printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* GFX Core Initialization */ @@ -1003,7 +1003,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 1 << 6 | 1 << 8 | 1 << 10); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk(BIOS_INFO, "misc 28 = %x\n", reg32); + printk(BIOS_DEBUG, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31); @@ -1021,7 +1021,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 0); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk(BIOS_INFO, "misc 28 = %x\n", reg32); + printk(BIOS_DEBUG, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31); @@ -1062,7 +1062,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* release hold training for device 2. GFX initialization is done. */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk(BIOS_INFO, "rs780_gfx_init step7.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step7.\n"); return; } @@ -1070,11 +1070,11 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.1 sets RCB timeout to be 25ms */ /* 5.9.12.2. RCB Cpl timeout on link down. */ set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19); - printk(BIOS_INFO, "rs780_gfx_init step5.9.12.1.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n"); /* step 5.9.12.3 disables slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk(BIOS_INFO, "rs780_gfx_init step5.9.12.3.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n"); /* step 5.9.12.4 sets DMA payload size to 64 bytes */ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); @@ -1096,7 +1096,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk(BIOS_INFO, "rs780_gfx_init step5.9.12.9.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n"); /* 5.9.12.10 Sets the timer in Config state from 20us to */ /* 5.9.12.11 De-asserts RX_EN in L0s. */ @@ -1169,15 +1169,14 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) if (cfg->gfx_lane_reversal) { set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); } - printk_info("rs780_gfx_init step1.\n"); - printk_info("rs780_gfx_init step2.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - printk_info("device = %x\n", dev->path.pci.devfn >> 3); - if((dev->path.pci.devfn >> 3) == 2) + printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); + if((dev->path.pci.devfn >> 3) == 2) { single_port_configuration(nb_dev, dev); - else{ + } else { set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ - printk_info("If dev3.., single port. Do nothing.\n"); + printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3 } break; @@ -1187,17 +1186,17 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); } - printk_info("rs780_gfx_init step1.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ /* AMD calls the configuration CrossFire */ set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs780_gfx_init step2.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); - printk_info("device = %x\n", dev->path.pci.devfn >> 3); + printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); dual_port_configuration(nb_dev, dev); break; default: - printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n"); + printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n"); break; } } diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c index c57bf0919b..652d6d00f7 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c +++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c @@ -133,7 +133,7 @@ static void i82801dx_power_options(device_t dev) reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ pci_write_config8(dev, GEN_PMCON_3, reg8); - printk_info("Set power %s after power failure.\n", state); + printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -147,10 +147,10 @@ static void i82801dx_power_options(device_t dev) nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - printk_info ("NMI sources enabled.\n"); + printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ } else { - printk_info ("NMI sources disabled.\n"); + printk(BIOS_INFO, "NMI sources disabled.\n"); reg8 |= ( 1 << 7); /* Disable NMI. */ } outb(reg8, 0x70); @@ -232,7 +232,7 @@ static void enable_hpet(struct device *dev) u32 reg32, hpet, val; /* Set HPET base address and enable it */ - printk_debug("Enabling HPET at 0x%x\n", HPET_ADDR); + printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR); reg32 = pci_read_config32(dev, GEN_CNTL); /* * Bit 17 is HPET enable bit. @@ -253,9 +253,9 @@ static void enable_hpet(struct device *dev) val &= 0x7; if ((val & 0x4) && (hpet == (val & 0x3))) { - printk_debug("HPET enabled at 0x%x\n", HPET_ADDR); + printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR); } else { - printk_err("HPET was not enabled correctly\n"); + printk(BIOS_WARNING, "HPET was not enabled correctly\n"); reg32 &= ~(1 << 17); /* Clear Enable */ pci_write_config32(dev, GEN_CNTL, reg32); } |