Uwe Hermann:

here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.
(part 1)



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 103 insertions, 103 deletions

diff --git a/src/southbridge/intel/i82801ca/cmos_failover.c b/src/southbridge/intel/i82801ca/cmos_failover.c
index 6197ef677a..8eb11c3f64 100644
--- a/src/southbridge/intel/i82801ca/cmos_failover.c
+++ b/src/southbridge/intel/i82801ca/cmos_failover.c
@@ -1,19 +1,19 @@
-//kind of cmos_err for ich3

-

-#include "i82801ca.h"

+//kind of cmos_err for ich3
+
+#include "i82801ca.h"
 
 static void check_cmos_failed(void) 
-{

+{
 #if HAVE_OPTION_TABLE
-	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);

+	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
 
 	if( byte & RTC_BATTERY_DEAD) {
-		// Set boot_option and last_boot to 'Fallback',

+		// Set boot_option and last_boot to 'Fallback',
 		// clear reboot_bits
         byte = cmos_read(RTC_BOOT_BYTE);
         byte &= 0x0c;
         byte |= MAX_REBOOT_CNT << 4;
         cmos_write(byte, RTC_BOOT_BYTE);
-    }

+    }
 #endif
 }
diff --git a/src/southbridge/intel/i82801ca/i82801ca.c b/src/southbridge/intel/i82801ca/i82801ca.c
index 27432d95fb..11ac82c329 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.c
+++ b/src/southbridge/intel/i82801ca/i82801ca.c
@@ -7,8 +7,8 @@
 
 void i82801ca_enable(device_t dev)
 {
-	unsigned int index = 0;

-	uint8_t bHasDisableBit = 0;

+	unsigned int index = 0;
+	uint8_t bHasDisableBit = 0;
 	uint16_t cur_disable_mask, new_disable_mask;
 
 //	all 82801ca devices are in bus 0
@@ -19,22 +19,22 @@ void i82801ca_enable(device_t dev)
 
 	// Calculate disable bit position for specified device:function
 	// NOTE: For ICH-3, only the following devices can be disabled:
-	//		 D31:F1, D31:F3, D31:F5, D31:F6, 

-	//		 D29:F0, D29:F1, D29:F2

+	//		 D31:F1, D31:F3, D31:F5, D31:F6, 
+	//		 D29:F0, D29:F1, D29:F2
 
     if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
-    	index = PCI_FUNC(dev->path.u.pci.devfn);

-

-		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))

-			bHasDisableBit = 1;

+    	index = PCI_FUNC(dev->path.u.pci.devfn);
+
+		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
+			bHasDisableBit = 1;
 
     } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
-    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);

-

-		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)

+    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
+
+		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
 			bHasDisableBit = 1;
     }
-

+
 	if (bHasDisableBit) {
 		cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
 		new_disable_mask = cur_disable_mask & ~(1<<index); 		// enable it
@@ -43,7 +43,7 @@ void i82801ca_enable(device_t dev)
 		}
 		if (new_disable_mask != cur_disable_mask) {
 			pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
-		}

+		}
 	}
 }
 
diff --git a/src/southbridge/intel/i82801ca/i82801ca.h b/src/southbridge/intel/i82801ca/i82801ca.h
index a5117f23b6..59056f29df 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.h
+++ b/src/southbridge/intel/i82801ca/i82801ca.h
@@ -1,10 +1,10 @@
 #ifndef I82801CA_H
 #define I82801CA_H
-

-#ifndef __ROMCC__

+
+#ifndef __ROMCC__
 #include "chip.h"
-extern void i82801ca_enable(device_t dev);

-#endif

+extern void i82801ca_enable(device_t dev);
+#endif
 
 
 #define PCI_DMA_CFG     0x90
@@ -26,37 +26,37 @@ extern void i82801ca_enable(device_t dev);
 #define FUNC_DIS        0xF2
 
 // GEN_PMCON_3 bits
-#define RTC_BATTERY_DEAD		(1<<2)

-#define RTC_POWER_FAILED		(1<<1)

+#define RTC_BATTERY_DEAD		(1<<2)
+#define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
-

-/********************************************************************/

-/*							IDE Controller                          */

-/********************************************************************/

-

-// PCI Configuration Space (D31:F1)

-#define IDE_TIM_PRI		0x40		// IDE timings, primary

-#define IDE_TIM_SEC		0x42		// IDE timings, secondary

-

-

-// IDE_TIM bits

-#define IDE_DECODE_ENABLE	(1<<15)

-

-/********************************************************************/

-/*								SMBus                               */

-/********************************************************************/

-

-// PCI Configuration Space (D31:F3)

+
+/********************************************************************/
+/*							IDE Controller                          */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F1)
+#define IDE_TIM_PRI		0x40		// IDE timings, primary
+#define IDE_TIM_SEC		0x42		// IDE timings, secondary
+
+
+// IDE_TIM bits
+#define IDE_DECODE_ENABLE	(1<<15)
+
+/********************************************************************/
+/*								SMBus                               */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20
-#define HOSTC		0x40

-

-// HOSTC bits

-#define I2C_EN		(1<<2)

-#define SMB_SMI_EN	(1<<1)

-#define HST_EN		(1<<0)

+#define HOSTC		0x40
+
+// HOSTC bits
+#define I2C_EN		(1<<2)
+#define SMB_SMI_EN	(1<<1)
+#define HST_EN		(1<<0)
 
 #define SMBUS_IO_BASE 0x1000
-

+
 // I/O registers (relative to SMBUS_IO_BASE)
 #define SMBHSTSTAT		0
 #define SMBHSTCTL		2
@@ -69,7 +69,7 @@ extern void i82801ca_enable(device_t dev);
 #define SMBSLVDATA		10
 #define SMLINK_PIN_CTL	14
 #define SMBUS_PIN_CTL	15 
-

+
 /* Between 1-10 seconds, We should never timeout normally 
  * Longer than this is just painful when a timeout condition occurs.
  */
diff --git a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
index 054af75089..c97dd63e2c 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
@@ -1,5 +1,5 @@
 #include <device/pci_ids.h>
-#include "i82801ca.h"

+#include "i82801ca.h"
 
 static void enable_smbus(void)
 {
diff --git a/src/southbridge/intel/i82801ca/i82801ca_ide.c b/src/southbridge/intel/i82801ca/i82801ca_ide.c
index 50539fc5f7..38700bd851 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_ide.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_ide.c
@@ -10,7 +10,7 @@ static void ide_init(struct device *dev)
 {
 	/* Enable ide devices so the linux ide driver will work */
 	uint16_t ideTimingConfig;
-	int enable_primary = 1;

+	int enable_primary = 1;
 	int enable_secondary = 1;
 
 	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
index 306d01a972..99d6803931 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
@@ -1,7 +1,7 @@
 /*
  * (C) 2003 Linux Networx, SuSE Linux AG
  * (C) 2004 Tyan Computer
- * (c) 2005 Digital Design Corporation

+ * (c) 2005 Digital Design Corporation
  */
 #include <console/console.h>
 #include <device/device.h>
@@ -14,14 +14,14 @@
 #include "i82801ca.h"
 
 #define NMI_OFF 0
-

-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL

-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON

-#endif

-

-#define MAINBOARD_POWER_OFF 0

-#define MAINBOARD_POWER_ON  1

-

+
+#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
 
 void i82801ca_enable_ioapic( struct device *dev) 
 {
@@ -60,20 +60,20 @@ void i82801ca_enable_serial_irqs( struct device *dev)
     pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
 }
 
-//----------------------------------------------------------------------------------

-// Function:    	i82801ca_lpc_route_dma

+//----------------------------------------------------------------------------------
+// Function:    	i82801ca_lpc_route_dma
 // Parameters:  	dev
 //					mask - identifies whether each channel should be used for PCI DMA
 //						   (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-//						   Channel 4 is not used (reserved). 

-// Return Value:	None

-// Description: 	Route all DMA channels to either PCI or LPC.

-//

+//						   Channel 4 is not used (reserved). 
+// Return Value:	None
+// Description: 	Route all DMA channels to either PCI or LPC.
+//
 void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) 
 {
     uint16_t dmaConfig;
     int channelIndex;
-

+
     dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
     dmaConfig &= 0x300;				// Preserve reserved bits
     for(channelIndex = 0; channelIndex < 8; channelIndex++) {
@@ -87,26 +87,26 @@ void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask)
 void i82801ca_rtc_init(struct device *dev)
 {
     uint32_t dword;
-    int rtc_failed;

-	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;

-    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);

+    int rtc_failed;
+	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
 
     rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
     if (rtc_failed) {
     	// Clear the RTC_BATTERY_DEAD bit, but preserve
-        // the RTC_POWER_FAILED, G3 state, and reserved bits

+        // the RTC_POWER_FAILED, G3 state, and reserved bits
 		// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
         pmcon3 &= ~RTC_POWER_FAILED;
-    }

-

-    get_option(&pwr_on, "power_on_after_fail");

-	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;

-	if (!pwr_on) {

-		pmcon3 |= SLEEP_AFTER_POWER_FAIL;

-	}

-	pci_write_config8(dev, GEN_PMCON_3, pmcon3);

-	printk_info("set power %s after power fail\n", 

-				 pwr_on ? "on" : "off");

+    }
+
+    get_option(&pwr_on, "power_on_after_fail");
+	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
+	if (!pwr_on) {
+		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
+	}
+	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
+	printk_info("set power %s after power fail\n", 
+				 pwr_on ? "on" : "off");
 
     // See if the Safe Mode jumper is set
     dword = pci_read_config32(dev, GEN_STS);
@@ -142,14 +142,14 @@ void i82801ca_1f0_misc(struct device *dev)
     // Enable access to the upper 128 byte bank of CMOS RAM
     pci_write_config8(dev, RTC_CONF, 0x04);
         
-    // Decode 0x3F8-0x3FF (COM1) for COMA port,

+    // Decode 0x3F8-0x3FF (COM1) for COMA port,
 	//		  0x2F8-0x2FF (COM2) for COMB
     pci_write_config8(dev, COM_DEC, 0x10);
-

-	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F

-	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7

 
-    // Enable COMA, COMB, LPT, floppy; 

+	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
+	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
+
+    // Enable COMA, COMB, LPT, floppy; 
 	// disable microcontroller, Super I/O, sound, gameport
     pci_write_config16(dev, LPC_EN, 0x000F);
 }
@@ -179,18 +179,18 @@ static void lpc_init(struct device *dev)
     pci_write_config8(dev, GEN_PMCON_3, byte);
     printk_info("set power %s after power fail\n", pwr_on?"on":"off");
 
-    /* Set up NMI on errors */

-    byte = inb(0x61);

-    byte &= ~(1 << 3); /* IOCHK# NMI Enable */

-    byte &= ~(1 << 2); /* PCI SERR# Enable */

-    outb(byte, 0x61);

-    byte = inb(0x70);

-    nmi_option = NMI_OFF;

-    get_option(&nmi_option, "nmi");

-    if (nmi_option) {			

-        byte &= ~(1 << 7); /* set NMI */

-        outb(byte, 0x70);

-    }

+    /* Set up NMI on errors */
+    byte = inb(0x61);
+    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+    byte &= ~(1 << 2); /* PCI SERR# Enable */
+    outb(byte, 0x61);
+    byte = inb(0x70);
+    nmi_option = NMI_OFF;
+    get_option(&nmi_option, "nmi");
+    if (nmi_option) {			
+        byte &= ~(1 << 7); /* set NMI */
+        outb(byte, 0x70);
+    }
 	
 	/* Initialize the real time clock */
 	i82801ca_rtc_init(dev);
diff --git a/src/southbridge/intel/i82801ca/i82801ca_smbus.c b/src/southbridge/intel/i82801ca/i82801ca_smbus.c
index ab95e69e70..0eceba7103 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_smbus.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_smbus.c
@@ -1,7 +1,7 @@
 #include <smbus.h>
 #include <pci.h>
 #include <arch/io.h>
-#include "i82801ca.h"

+#include "i82801ca.h"
 
 #define PM_BUS 0
 #define PM_DEVFN PCI_DEVFN(0x1f,3)
@@ -9,7 +9,7 @@
 void smbus_enable(void)
 {
 	/* iobase addr */
-	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 

+	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 
 							   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
 	/* smbus enable */
 	pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);