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authorElyes Haouas <ehaouas@noos.fr>2022-02-11 21:51:23 +0100
committerMartin L Roth <gaumless@tutanota.com>2022-05-16 02:57:51 +0000
commite37806766feb667be25ada02ada2b796131ca6d0 (patch)
treee9c83782171faf9271a6d6e1feda3e4c0cd49df6 /src/southbridge
parent9ca1ef96aef59d0e03610566f90f028e9c487712 (diff)
sb/amd/*/*/acpi: Reduce stylistic differences
Change-Id: I1375b1d18113000b31266030fd7115e23d7cce5f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl2
-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/audio.asl2
-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/fch.asl28
-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/lpc.asl1
-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/usb.asl6
5 files changed, 23 insertions, 16 deletions
diff --git a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
index 757b193c04..6fe5e33cb8 100644
--- a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
+++ b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
@@ -20,7 +20,7 @@ Method(WACK, 0)
{
Local0 = 0
Local1 = 50
- While ((Local0 != 0xFA) && (Local1 > 0)) {
+ While ((Local0 != 0xfa) && (Local1 > 0)) {
Local0 = MRG0
Sleep(10)
Local1--
diff --git a/src/southbridge/amd/cimx/sb800/acpi/audio.asl b/src/southbridge/amd/cimx/sb800/acpi/audio.asl
index 0adb13687d..0d5f00d33c 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/audio.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/audio.asl
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-Device(AZHD) {
+Device(AZHD) { /* 0:14.2 - HD Audio */
Name(_ADR, 0x00140002)
OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
Field(AZPD, AnyAcc, NoLock, Preserve) {
diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
index 7cf8bb8a59..5527660255 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
@@ -115,13 +115,13 @@ Method(_CRS, 0) {
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
/*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
MM1B = TOM1
Local0 = 0x10000000 << 4
Local0 -= TOM1
@@ -131,13 +131,13 @@ Method(_CRS, 0) {
} /* end of Method(_SB.PCI0._CRS) */
/*
-*
-* FIRST METHOD CALLED UPON BOOT
-*
-* 1. If debugging, print current OS and ACPI interpreter.
-* 2. Get PCI Interrupt routing from ACPI VSM, this
-* value is based on user choice in BIOS setup.
-*/
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
Method(_INI, 0) {
/* DBGO("\\_SB\\_INI\n") */
/* DBGO(" DSDT.ASL code from ") */
diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
index dc72061be0..151b015074 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+/* 0:14.3 - LPC */
Device(LIBR) {
Name(_ADR, 0x00140003)
diff --git a/src/southbridge/amd/cimx/sb800/acpi/usb.asl b/src/southbridge/amd/cimx/sb800/acpi/usb.asl
index f174ddb22e..35c8c7e459 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/usb.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/usb.asl
@@ -1,30 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+/* 0:12.0 - OHCI */
Device(UOH1) {
Name(_ADR, 0x00120000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH1 */
+/* 0:12.2 - EHCI */
Device(UOH2) {
Name(_ADR, 0x00120002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH2 */
+/* 0:13.0 - OHCI */
Device(UOH3) {
Name(_ADR, 0x00130000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH3 */
+/* 0:13.2 - EHCI */
Device(UOH4) {
Name(_ADR, 0x00130002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH4 */
+/* 0:16.0 - OHCI */
Device(UOH5) {
Name(_ADR, 0x00160000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
+/* 0:16.2 - EHCI */
Device(UOH6) {
Name(_ADR, 0x00160002)
Name(_PRW, Package() {0x0B, 3})