southbridge/intel/bd82x6x: transition away from device_t

Replace the use of the old device_t definition inside
southbridge/intel/bd82x6x.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

Change-Id: I7166bfab7904f80b745855d3bbcfb910cbc89f56
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16407
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

5 files changed, 10 insertions, 8 deletions

diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 2b174c787a..9f74fdd45f 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -23,7 +23,7 @@
 
 void enable_smbus(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	/* Set the SMBus device statically. */
 	dev = PCI_DEV(0x0, 0x1f, 0x3);
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index b2fbd69e27..a5c63b617f 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -38,7 +38,7 @@ static uint16_t read16p (uintptr_t addr)
    which is done at the end of raminit.  */
 void early_thermal_init(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 	msr_t msr;
 
 	dev = PCI_DEV(0x0, 0x1f, 0x6);
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 974abb1368..51fdd2e76d 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -30,11 +30,12 @@
 int pch_silicon_revision(void)
 {
 	static int pch_revision_id = -1;
-	device_t dev;
 
-#ifdef __SMM__
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev;
 	dev = PCI_DEV(0, 0x1f, 0);
 #else
+	device_t dev;
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 #endif
 
@@ -46,11 +47,12 @@ int pch_silicon_revision(void)
 int pch_silicon_type(void)
 {
 	static int pch_type = -1;
-	device_t dev;
 
-#ifdef __SMM__
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev;
 	dev = PCI_DEV(0, 0x1f, 0);
 #else
+	device_t dev;
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 #endif
 
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index f22fed59c3..1977c8f9d2 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,7 +66,7 @@ void intel_pch_finalize_smm(void);
 
 #if !defined(__ASSEMBLER__)
 #if !defined(__PRE_RAM__)
-#if !defined(__SMM__)
+#if !defined(__SIMPLE_DEVICE__)
 #include "chip.h"
 void pch_enable(device_t dev);
 #endif
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 0478285195..71ebb6e0e6 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -278,7 +278,7 @@ static void busmaster_disable_on_bus(int bus)
 	for (slot = 0; slot < 0x20; slot++) {
 		for (func = 0; func < 8; func++) {
 			u32 reg32;
-			device_t dev = PCI_DEV(bus, slot, func);
+			pci_devfn_t dev = PCI_DEV(bus, slot, func);
 
 			val = pci_read_config32(dev, PCI_VENDOR_ID);