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authorTim Wawrzynczak <twawrzynczak@chromium.org>2022-01-20 14:06:29 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-01-24 16:28:12 +0000
commitb3cd55b22458921ed39b74062a66bf092bf07c3c (patch)
tree895b2a1b0fba079654471f1aec2ec20069c67ed4 /src/southbridge
parent6dfa528af9d2f539b154ce812385cd085251480c (diff)
soc/intel/common/block/pcie/rtd3: Fix PMC IPC method for CPU PCIe RP
When calling get_pcie_rp_pmc_idx(), the following code checked the return value to see if it was negative or `> CONFIG_MAX_ROOT_PORTS`. However, the expected return value for CPU PCIe RPs is above MAX_ROOT_PORTS. Since the static, local function is intended to return -1 or a valid value, drop the check for `> CONFIG_MAX_ROOT_PORTS`. Change-Id: I2039273ad246884cd8736a7f0355e621a706a526 Fixes: b6a15a7 ("soc/intel/common/block/pcie/rtd3: Update ACPI Update ACPI methods for CPU PCIe RPs") Tested-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
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