diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 18:40:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-13 09:14:20 +0000 |
| commit | b236352281405c3a6860b51af8acfd2e78c45e78 (patch) | |
| tree | b01d63b408445343948e40713ff6f541ea2a1319 /src/southbridge | |
| parent | 0d92271d2cfcb98712b9e0a0c7c295bbe929b4ab (diff) | |
sb/intel/i82801gx: Add a function to set up BAR
This removes some of the sb code in the nb.
Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801gx/bootblock_gcc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 12 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 1 |
3 files changed, 14 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c index 063a461e43..4c464ff920 100644 --- a/src/southbridge/intel/i82801gx/bootblock_gcc.c +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -32,9 +32,7 @@ void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + i82801gx_setup_bars(); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 533aaefe14..7f5f442333 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <stdint.h> #include <device/pci_ops.h> #include "i82801gx.h" #include "chip.h" @@ -50,3 +51,14 @@ void i82801gx_lpc_setup(void) pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); } + +void i82801gx_setup_bars(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); + + pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 259fb49f54..9eea262997 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,6 +41,7 @@ void i82801gx_enable(struct device *dev); void enable_smbus(void); void i82801gx_lpc_setup(void); +void i82801gx_setup_bars(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); |