diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 13:48:46 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-05-20 16:03:54 +0000 |
| commit | 9ffb57c6781676d5d8f54e3dba59b01a60c53c2e (patch) | |
| tree | 252f671a9bee27efa7bb2496b86bdbef1fd2fcba /src/southbridge | |
| parent | 581fd082e2e063c9eee8e78ab16f54229c062f7c (diff) | |
sb/intel/lynxpoint: Relocate SATA clock gating write
Do it in the same place as Broadwell.
Tested on out-of-tree Compal LA-A992P, SATA still works.
Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47034
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/sata.c | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fc287b0f80..fb421451f8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -565,8 +565,6 @@ static void enable_lp_clock_gating(struct device *dev) RCBA32_OR(0x3434, 0x7); // LP LPC - RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA - RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic pch_iobp_update(0xCF000000, ~0, 0x00007001); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 2a356004aa..1b69b8099f 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -187,6 +187,7 @@ static void sata_init(struct device *dev) if (pch_is_lp()) { sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); } reg32 = pci_read_config32(dev, 0x300); |