diff options
| author | Ronald G. Minnich <rminnich@gmail.com> | 2003-10-22 21:54:19 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2003-10-22 21:54:19 +0000 |
| commit | 88fbae24bc83b46b1a1f2ba88643462053dae5cf (patch) | |
| tree | a2d30095bb023f0315a3c21d5016381df0801ee9 /src/southbridge | |
| parent | 7f1105c431d8425cb1027e8c75787c826425c33d (diff) | |
fixes for EPIA.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.c | 1 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_smbus.c | 28 |
2 files changed, 14 insertions, 15 deletions
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index 55e833d7b5..1719fb207d 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -437,7 +437,6 @@ static void southbridge_init(struct chip *chip, enum chip_pass pass) case CONF_PASS_POST_PCI: vt8231_init(conf); - printk_err("FUCK! ROUTING FIXUP!\n"); pci_routing_fixup(); break; diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c index e419d59b63..1888176144 100644 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c @@ -47,8 +47,8 @@ static void enable_smbus(void) c = pci_read_config8(dev, 4); c |= 1; pci_write_config8(dev, 4, c); - print_err_hex8(c); - print_err(" is the comm register\n"); + print_debug_hex8(c); + print_debug(" is the comm register\r\n"); print_debug("SMBus controller enabled\r\n"); } @@ -69,9 +69,9 @@ static int smbus_wait_until_ready(void) smbus_delay(); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); while((c & 1) == 1) { - print_err("c is "); - print_err_hex8(c); - print_err("\n"); + print_debug("c is "); + print_debug_hex8(c); + print_debug("\r\n"); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); /* nop */ } @@ -88,9 +88,9 @@ void smbus_reset(void) outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); smbus_wait_until_ready(); - print_err("After reset status "); - print_err_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_err("\n"); + print_debug("After reset status "); + print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); + print_debug("\r\n"); } @@ -117,21 +117,21 @@ static void smbus_print_error(unsigned char host_status_register) print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\n"); + print_err("\r\n"); if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\n"); + print_err("Bus Error\r\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\n"); + print_err("Device Error\r\n"); } if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\n"); + print_err("Interrupt/SMI# was Successful Completion\r\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\n"); + print_err("Host Busy\r\n"); } } |