diff options
| author | Keith Hui <buurin@gmail.com> | 2023-11-27 00:15:59 -0500 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-12-23 16:44:20 +0000 |
| commit | 885e8cb36aabc5b7023c9fb4d38c0553b77a7bb0 (patch) | |
| tree | 43c0004bdac2badb8e81aed04e62872cdf111a42 /src/southbridge | |
| parent | 25620524237ec4665f5a462fe6dbc4dcef313870 (diff) | |
sb/intel/bd82x6x: Honor POST code Kconfig option
This southbridge can route POST codes written to port 0x80 to either
LPC or PCI, but currently always route them to LPC. Change it so that
POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is
selected, LPC otherwise.
Rename the static function because POST codes no longer always go to
LPC.
Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/bootblock.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7e52..3260021d08 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -5,10 +5,13 @@ #include <southbridge/intel/common/early_spi.h> #include "pch.h" -static void enable_port80_on_lpc(void) +static void setup_port80(void) { - /* Enable port 80 POST on LPC */ - RCBA32(GCS) &= (~0x04); + /* Enable port 80 POST */ + if (CONFIG(POST_DEVICE_PCI_PCIE)) + RCBA32(GCS) |= 0x04; /* ... on PCI(e) */ + else + RCBA32(GCS) &= (~0x04); /* ... on LPC */ } static void set_spi_speed(void) @@ -37,7 +40,7 @@ void bootblock_early_southbridge_init(void) early_pch_init(); - enable_port80_on_lpc(); + setup_port80(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ |