diff options
| author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-04 14:26:26 -0600 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-05 21:53:55 +0100 |
| commit | 7ad4dc5e9914e927a827ce48a030d2d04e7ec792 (patch) | |
| tree | 1a279d488f9730ff954a7783dfde95c275c1a09c /src/southbridge | |
| parent | d502dc092a26726472fc5871c77ebff192be4cb8 (diff) | |
src/amd: Add common definition of AMD ACPI MMIO address
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18032
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/common/amd_defs.h | 22 | ||||
| -rw-r--r-- | src/southbridge/amd/sb800/early_setup.c | 5 |
2 files changed, 25 insertions, 2 deletions
diff --git a/src/southbridge/amd/common/amd_defs.h b/src/southbridge/amd/common/amd_defs.h new file mode 100644 index 0000000000..55db30f409 --- /dev/null +++ b/src/southbridge/amd/common/amd_defs.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Raptor Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _AMD_SB_DEFS_H_ +#define _AMD_SB_DEFS_H_ + +#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul + +#endif diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 54e6ada79b..7ac6ec85fe 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -19,6 +19,7 @@ #include <reset.h> #include <arch/acpi.h> #include <arch/cpu.h> +#include <southbridge/amd/common/amd_defs.h> #include <cbmem.h> #include "sb800.h" #include "smbus.c" @@ -107,8 +108,8 @@ void sb800_clk_output_48Mhz(void) reg8 &= ~(1 << 1); pmio_write(0x24, reg8); - *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ + *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) |= 1 << 1; /* 48Mhz */ } /*************************************** * Legacy devices are mapped to LPC space. |