sb/amd/sb800: Drop support

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I1c25837f1ba05ecd58309b63a471001f4aee2fff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36968
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

21 files changed, 0 insertions, 3359 deletions

diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig
deleted file mode 100644
index 245a9f2272..0000000000
--- a/src/southbridge/amd/sb800/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config SOUTHBRIDGE_AMD_SB800
-	bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-
-if SOUTHBRIDGE_AMD_SB800
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/sb800/bootblock.c"
-
-config EHCI_BAR
-	hex
-	default 0xfef00000
-
-endif # SOUTHBRIDGE_AMD_SB800
diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc
deleted file mode 100644
index 276ca29acd..0000000000
--- a/src/southbridge/amd/sb800/Makefile.inc
+++ /dev/null
@@ -1,22 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y)
-
-ramstage-y += sb800.c
-ramstage-y += usb.c
-ramstage-y += lpc.c
-ramstage-y += sm.c
-ramstage-y += ide.c
-ramstage-y += sata.c
-ramstage-y += hda.c
-ramstage-y += pci.c
-ramstage-y += pcie.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
-ramstage-y += reset.c
-
-bootblock-y += enable_usbdebug.c
-romstage-y += enable_usbdebug.c
-ramstage-y += enable_usbdebug.c
-
-romstage-y += ramtop.c
-ramstage-y += ramtop.c
-
-endif
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
deleted file mode 100644
index 0b3486406e..0000000000
--- a/src/southbridge/amd/sb800/bootblock.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_ops.h>
-
-/*
- * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
- *
- * Hardware should enable LPC ROM by pin straps. This function does not
- * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
- *
- * The SB800 power-on default is to map 512K ROM space.
- *
- */
-static void sb800_enable_rom(void)
-{
-	u8 reg8;
-	pci_devfn_t dev;
-
-	dev = PCI_DEV(0, 0x14, 3);
-
-	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, 0x48);
-	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, 0x48, reg8);
-
-	/* LPC ROM address range 1: */
-	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_io_write_config16(dev, 0x68, 0x000e);
-	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_io_write_config16(dev, 0x6a, 0x000f);
-
-	/* LPC ROM address range 2: */
-	/*
-	 * Enable LPC ROM range start at:
-	 * 0xfff8(0000): 512KB
-	 * 0xfff0(0000): 1MB
-	 * 0xffe0(0000): 2MB
-	 * 0xffc0(0000): 4MB
-	 */
-	pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
-	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_io_write_config16(dev, 0x6e, 0xffff);
-}
-
-static void bootblock_southbridge_init(void)
-{
-	sb800_enable_rom();
-}
diff --git a/src/southbridge/amd/sb800/chip.h b/src/southbridge/amd/sb800/chip.h
deleted file mode 100644
index f77397744f..0000000000
--- a/src/southbridge/amd/sb800/chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef SB800_CHIP_H
-#define SB800_CHIP_H
-
-struct southbridge_amd_sb800_config
-{
-	u32 ide0_enable : 1;
-	u32 sata0_enable : 1;
-	u32 boot_switch_sata_ide : 1;
-	u32 hda_viddid;
-	u8  gpp_configuration;
-};
-
-#endif /* SB800_CHIP_H */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
deleted file mode 100644
index b549c5e17c..0000000000
--- a/src/southbridge/amd/sb800/early_setup.c
+++ /dev/null
@@ -1,662 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SB800_EARLY_SETUP_C_
-#define _SB800_EARLY_SETUP_C_
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-#include <reset.h>
-#include <southbridge/amd/common/amd_defs.h>
-#include <southbridge/amd/common/reset.h>
-
-#include "sb800.h"
-#include "smbus.c"
-
-#define SMBUS_IO_BASE 0x6000	/* Is it a temporary SMBus I/O base address? */
-	 /*SIZE 0x40 */
-
-static void pmio_write(u8 reg, u8 value)
-{
-	outb(reg, PM_INDEX);
-	outb(value, PM_INDEX + 1);
-}
-
-static u8 pmio_read(u8 reg)
-{
-	outb(reg, PM_INDEX);
-	return inb(PM_INDEX + 1);
-}
-
-static void sb800_acpi_init(void)
-{
-	pmio_write(0x60, ACPI_PM_EVT_BLK & 0xFF);
-	pmio_write(0x61, ACPI_PM_EVT_BLK >> 8);
-	pmio_write(0x62, ACPI_PM1_CNT_BLK & 0xFF);
-	pmio_write(0x63, ACPI_PM1_CNT_BLK >> 8);
-	pmio_write(0x64, ACPI_PM_TMR_BLK & 0xFF);
-	pmio_write(0x65, ACPI_PM_TMR_BLK >> 8);
-	pmio_write(0x68, ACPI_GPE0_BLK & 0xFF);
-	pmio_write(0x69, ACPI_GPE0_BLK >> 8);
-
-	/* CpuControl is in \_PR.CP00, 6 bytes */
-	pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF);
-	pmio_write(0x67, ACPI_CPU_CONTROL >> 8);
-
-	pmio_write(0x6A, 0xB0);	/* AcpiSmiCmdLo */
-	pmio_write(0x6B, 0);	/* AcpiSmiCmdHi */
-
-	pmio_write(0x6E, 0xB8);	/* AcpiPmaCntBlkLo */
-	pmio_write(0x6F, 0);	/* AcpiPmaCntBlkHi */
-
-	pmio_write(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
-	pmio_write(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
-	pmio_write(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
-					* the contents of the PM registers at
-					* index 60-6B to decode ACPI I/O address.
-					* AcpiSmiEn & SmiCmdEn*/
-	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
-}
-
-/* RPR 2.28 Get SB ASIC Revision.*/
-static u8 get_sb800_revision(void)
-{
-	pci_devfn_t dev;
-	u8 rev_id;
-	u8 rev = 0;
-
-	/* if (rev != 0) return rev; */
-
-	dev = PCI_DEV(0, 0x14, 0);
-
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\n");
-		/* NOT REACHED */
-	}
-	rev_id =  pci_read_config8(dev, 0x08);
-
-	if (rev_id == 0x40) {
-		rev = REV_SB800_A11;
-	} else if (rev_id == 0x41) {
-		rev = REV_SB800_A12;
-	} else {
-		die("It is not SB800 or SB810\r\n");
-	}
-
-	return rev;
-}
-
-void sb800_clk_output_48Mhz(void)
-{
-	/* AcpiMMioDecodeEn */
-	u8 reg8;
-	reg8 = pmio_read(0x24);
-	reg8 |= 1;
-	reg8 &= ~(1 << 1);
-	pmio_write(0x24, reg8);
-
-	*(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
-	*(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) |= 1 << 1; /* 48Mhz */
-}
-/***************************************
-* Legacy devices are mapped to LPC space.
-*	Serial port 0
-*	KBC Port
-*	ACPI Micro-controller port
-*	LPC ROM size
-*	This function does not change port 0x80 decoding.
-*	Console output through any port besides 0x3f8 is unsupported.
-*	If you use FWH ROMs, you have to setup IDSEL.
-***************************************/
-static void sb800_lpc_init(void)
-{
-	u8 reg8;
-	pci_devfn_t dev;
-
-	dev = PCI_DEV(0, 0x14, 0); /* SMBUS controller */
-	/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
-	 * This bit has no meaning if debug strap is not enabled. So if the
-	 * board keeps rebooting and the code fails to reach here, we could
-	 * disable the debug strap first. */
-	reg8 = pmio_read(0x44+3);
-	reg8 |= 1 << 7;
-	pmio_write(0x44+3, reg8);
-
-	/* Enable lpc controller */
-	reg8 = pmio_read(0xEC);
-	reg8 |= 1 << 0;
-	pmio_write(0xEC, reg8);
-
-	dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */
-	/* Decode port 0x3f8-0x3ff (Serial 0) */
-	//#warning Serial port decode on LPC is hardcoded to 0x3f8
-	reg8 = pci_read_config8(dev, 0x44);
-	reg8 |= 1 << 6;
-	pci_write_config8(dev, 0x44, reg8);
-
-	/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
-	reg8 = pci_read_config8(dev, 0x47);
-	reg8 |= (1 << 5) | (1 << 6);
-	pci_write_config8(dev, 0x47, reg8);
-
-	/* SuperIO, LPC ROM */
-	reg8 = pci_read_config8(dev, 0x48);
-	/* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
-	reg8 |= (1 << 1) | (1 << 0);
-	/* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
-	reg8 |= (1 << 3) | (1 << 4);
-	/* Decode port 0x70-0x73 (RTC) */
-	reg8 |= 1 << 6;
-	pci_write_config8(dev, 0x48, reg8);
-}
-
-/* what is its usage? */
-u32 get_sbdn(u32 bus)
-{
-	pci_devfn_t dev;
-
-	/* Find the device. */
-	dev = PCI_DEV(bus, 0x14, 0);
-	return (dev >> 15) & 0x1f;
-}
-
-static u8 dual_core(void)
-{
-	return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0;
-}
-
-/*
- * RPR 2.6 C-state and VID/FID change for the K8 platform.
- */
-static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
-{
-	u8 byte;
-	byte = pmio_read(0x80);
-	if (dual_core())
-		byte |= 1 << 2 | 1 << 1;
-	byte |= 1 << 3;
-	byte |= 1 << 4;
-	byte &= ~(1 << 7);
-	pmio_write(0x80, byte);
-
-	byte = pmio_read(0x7E);
-	byte |= 1 << 6;
-	byte &= ~(1 << 2);
-	pmio_write(0x7E, byte);
-
-	pmio_write(0x94, 0x01);
-
-	byte = pmio_read(0x89);
-	byte |= 1 << 4;
-	pmio_write(0x89, byte);
-
-	byte = pmio_read(0x9b);
-	byte &= ~(7 << 4);
-	byte |= 1 << 4;
-	pmio_write(0x9b, byte);
-
-	pmio_write(0x99, 0x10);
-
-	pmio_write(0x9A, 0x00);
-	pmio_write(0x96, 0x10);
-	pmio_write(0x97, 0x00);
-
-	byte = pmio_read(0x81);
-	byte &= ~(1 << 1);
-	pmio_write(0x81, byte);
-}
-
-void do_board_reset(void)
-{
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-void do_soft_reset(void)
-{
-	set_bios_reset();
-	/* link reset */
-	outb(0x06, 0x0cf9);
-}
-
-void sb800_pci_port80(void)
-{
-	u8 byte;
-	pci_devfn_t dev;
-
-	/* P2P Bridge */
-	dev = PCI_DEV(0, 0x14, 4);
-
-	/* Chip Control: Enable subtractive decoding */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
-
-	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4B, byte);
-
-	/* The same IO Base and IO Limit here is meaningful because we set the
-	 * bridge to be subtractive. During early setup stage, we have to make
-	 * sure that data can go through port 0x80.
-	 */
-	/* IO Base: 0xf000 */
-	byte = pci_read_config8(dev, 0x1C);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1C, byte);
-
-	/* IO Limit: 0xf000 */
-	byte = pci_read_config8(dev, 0x1D);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1D, byte);
-
-	/* PCI Command: Enable IO response */
-	byte = pci_read_config8(dev, 0x04);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x04, byte);
-
-	/* LPC controller */
-	dev = PCI_DEV(0, 0x14, 3);
-
-	byte = pci_read_config8(dev, 0x4A);
-	byte &= ~(1 << 5);	/* disable lpc port 80 */
-	pci_write_config8(dev, 0x4A, byte);
-}
-
-#define BIT0	(1 << 0)
-#define BIT1	(1 << 1)
-#define BIT2	(1 << 2)
-#define BIT3	(1 << 3)
-#define BIT4	(1 << 4)
-#define BIT5	(1 << 5)
-#define BIT6	(1 << 6)
-#define BIT7	(1 << 7)
-
-struct pm_entry {
-	u8	port;
-	u8	mask;
-	u8	bit;
-};
-struct pm_entry const pm_table[] =
-{
-	{0x5D, 0x00, BIT0},
-	{0xD2, 0xCF, BIT4 + BIT5},
-	{0x12, 0x00, BIT0},
-	{0x28, 0xFF, BIT0},
-	{0x44 + 3, 0x7F, BIT7},
-	{0x48, 0xFF, BIT0},
-	{0x00, 0xFF, 0x0E},
-	{0x00 + 2, 0xFF, 0x40},
-	{0x00 + 3, 0xFF, 0x08},
-	{0x34, 0xEF, BIT0 + BIT1},
-	{0xEC, 0xFD, BIT1},
-	{0x5B, 0xF9, BIT1 + BIT2},
-	{0x08, 0xFE, BIT2 + BIT4},
-	{0x08 + 1, 0xFF, BIT0},
-	{0x54, 0x00, BIT4 + BIT7},
-	{0x04 + 3, 0xFD, BIT1},
-	{0x74, 0xF6, BIT0 + BIT3},
-	{0xF0, ~BIT2, 0x00},
-	{0xF8,     0x00, 0x6C},
-	{0xF8 + 1, 0x00, 0x27},
-	{0xF8 + 2, 0x00, 0x00},
-	{0xC4, 0xFE, 0x14},
-	{0xC0 + 2, 0xBF, 0x40},
-	{0xBE, 0xDD, BIT5},
-	// HPET workaround
-	{0x54 + 3, 0xFC, BIT0 + BIT1},
-	{0x54 + 2, 0x7F, BIT7},
-	{0x54 + 2, 0x7F, 0x00},
-	{0xC4, ~(BIT2 + BIT4), BIT2 + BIT4},
-	{0xC0, 0, 0xF9},
-	{0xC0 + 1, 0x04, 0x03},
-	{0xC2, 0x20, 0x58},
-	{0xC2 + 1, 0, 0x40},
-	{0xC2, ~(BIT4), BIT4},
-	{0x74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
-	{0xDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
-	{0xDE, ~BIT4, BIT4},
-	{0xBA, ~BIT3, BIT3},
-	{0xBA + 1, ~BIT6, BIT6},
-	{0xBC, ~BIT1, BIT1},
-	{0xED, ~(BIT0 + BIT1), 0},
-	{0xDC, 0x7C, BIT0},
-//  {0xFF, 0xFF, 0xFF},
-};
-
-void sb800_lpc_port80(void)
-{
-	u8 byte;
-	pci_devfn_t dev;
-
-	/* Enable LPC controller */
-	byte = pmio_read(0xEC);
-	byte |= 1 << 0;
-	pmio_write(0xEC, byte);
-
-	/* Enable port 80 LPC decode in pci function 3 configuration space. */
-	dev = PCI_DEV(0, 0x14, 3);
-	byte = pci_read_config8(dev, 0x4a);
-	byte |= 1 << 5;		/* enable port 80 */
-	pci_write_config8(dev, 0x4a, byte);
-}
-
-/* sbDevicesPorInitTable */
-static void sb800_devices_por_init(void)
-{
-	pci_devfn_t dev;
-	u8 byte;
-
-	printk(BIOS_INFO, "sb800_devices_por_init()\n");
-	/* SMBus Device, BDF:0-20-0 */
-	printk(BIOS_INFO, "sb800_devices_por_init(): SMBus Device, BDF:0-20-0\n");
-	dev = PCI_DEV(0, 0x14, 0);
-
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\n");
-		/* NOT REACHED */
-	}
-	printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n",
-		    get_sb800_revision());
-
-	/* sbPorAtStartOfTblCfg */
-	/* rpr 4.1.Set A-Link bridge access address.
-	 * This is an I/O address. The I/O address must be on 16-byte boundary.  */
-	//pci_write_config32(dev, 0xf0, AB_INDX);
-	pmio_write(0xE0, AB_INDX & 0xFF);
-	pmio_write(0xE1, (AB_INDX >> 8) & 0xFF);
-	pmio_write(0xE2, (AB_INDX >> 16) & 0xFF);
-	pmio_write(0xE3, (AB_INDX >> 24) & 0xFF);
-
-	/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
-	/* 4.2:Enables the SB800 to send transactions upstream over A-Link Express interface. */
-	axcfg_reg(0x04, 1 << 2, 1 << 2);
-	//axindxc_reg(0x21, 0xff, 0);
-
-	/* 4.15:Enabling Non-Posted Memory Write for the K8 Platform */
-	axindxc_reg(0x10, 1 << 9, 1 << 9);
-	/* END of sbPorAtStartOfTblCfg */
-
-	/* sbDevicesPorInitTables */
-	/* set smbus iobase */
-	//pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
-	/* The base address of SMBUS is set in a different way with sb700. */
-	byte = (SMBUS_IO_BASE & 0xFF) | 1;
-	pmio_write(0x2c, byte & 0xFF);
-	pmio_write(0x2d, SMBUS_IO_BASE >> 8);
-
-	/* AcpiMMioDecodeEn */
-	byte = pmio_read(0x24);
-	byte |= 1;
-	byte &= ~(1 << 1);
-	pmio_write(0x24, byte);
-	/* enable smbus controller interface */
-	//byte = pci_read_config8(dev, 0xd2);
-	//byte |= (1 << 0);
-	//pci_write_config8(dev, 0xd2, byte);
-
-	/* KB2RstEnable */
-	//pci_write_config8(dev, 0x40, 0x44);
-
-	/* Enable ISA Address 0-960K decoding */
-	//pci_write_config8(dev, 0x48, 0x0f);
-
-	/* Enable ISA  Address 0xC0000-0xDFFFF decode */
-	//pci_write_config8(dev, 0x49, 0xff);
-
-	/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
-	//byte = pci_read_config8(dev, 0x41);
-	//byte &= 0x80;
-	//byte |= 0x33;
-	//pci_write_config8(dev, 0x41, byte);
-
-	/* Legacy DMA Prefetch Enhancement, CIM masked it. */
-	/* pci_write_config8(dev, 0x43, 0x1); */
-
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-	/* IDE Device, BDF:0-20-1 */
-	printk(BIOS_INFO, "sb800_devices_por_init(): IDE Device, BDF:0-20-1\n");
-	dev = PCI_DEV(0, 0x14, 1);
-	/* Disable prefetch */
-	byte = pci_read_config8(dev, 0x63);
-	byte |= 0x1;
-	pci_write_config8(dev, 0x63, byte);
-
-	/* LPC Device, BDF:0-20-3 */
-	printk(BIOS_INFO, "sb800_devices_por_init(): LPC Device, BDF:0-20-3\n");
-	dev = PCI_DEV(0, 0x14, 3);
-	/* DMA enable */
-	pci_write_config8(dev, 0x40, 0x04);
-
-	/* LPC Sync Timeout */
-	pci_write_config8(dev, 0x49, 0xFF);
-
-	/* Set LPC ROM size, it has been done in sb800_lpc_init().
-	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
-	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
-	 * pci_write_config16(dev, 0x68, 0x000e)
-	 * pci_write_config16(dev, 0x6c, 0xfff0);*/
-
-	/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
-	pci_write_config8(dev, 0x7C, 0x05);
-
-	/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
-	 */
-	printk(BIOS_INFO, "sb800_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
-	dev = PCI_DEV(0, 0x14, 4);
-
-	/* Arbiter enable. */
-	pci_write_config8(dev, 0x43, 0xff);
-
-	/* Set PCDMA request into height priority list. */
-	/* pci_write_config8(dev, 0x49, 0x1); */
-
-	pci_write_config8(dev, 0x40, 0x26);
-
-	pci_write_config8(dev, 0x0d, 0x40);
-	pci_write_config8(dev, 0x1b, 0x40);
-	/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
-	pci_write_config8(dev, 0x50, 0x01);
-
-	/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
-	printk(BIOS_INFO, "sb800_devices_por_init(): SATA Device, BDF:0-18-0\n");
-	dev = PCI_DEV(0, 0x11, 0);
-
-	/*PHY Global Control*/
-	pci_write_config16(dev, 0x86, 0x2C00);
-}
-
-/* sbPmioPorInitTable, Pre-initializing PMIO register space
-* The power management (PM) block is resident in the PCI/LPC/ISA bridge.
-* The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7.
-* The index address is first programmed into IO reg 0xcd6.
-* Read or write values are accessed through IO reg 0xcd7.
-*/
-#if 0
-static void sb800_pmio_por_init(void)
-{
-	u8 byte, i;
-
-	printk(BIOS_INFO, "sb800_pmio_por_init()\n");
-
-	byte = pmio_read(0xD2);
-	byte |= 3 << 4;
-	pmio_write(0xD2, byte);
-
-	byte = pmio_read(0x5D);
-	byte &= 3;
-	byte |= 1;
-	pmio_write(0x5D, byte);
-
-	/* Watch Dog Timer Control
-	 * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
-	 * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
-	 */
-	pmio_write(0x6c, 0xf0);
-	pmio_write(0x6d, 0x00);
-	pmio_write(0x6e, 0xc0);
-	pmio_write(0x6f, 0xfe);
-
-	/* rpr2.15: Enabling Spread Spectrum */
-	byte = pmio_read(0x42);
-	byte |= 1 << 7;
-	pmio_write(0x42, byte);
-	/* TODO: Check if it is necessary. IDE reset */
-	byte = pmio_read(0xB2);
-	byte |= 1 << 0;
-	pmio_write(0xB2, byte);
-
-	for (i = 0; i < sizeof(pm_table)/sizeof(struct pm_entry); i++) {
-		byte = pmio_read(pm_table[i].port);
-		byte &= pm_table[i].mask;
-		byte |= pm_table[i].bit;
-		pmio_write(pm_table[i].port, byte);
-	}
-	pmio_write(0x00, 0x0E);
-	pmio_write(0x01, 0x00);
-	pmio_write(0x02, 0x4F);
-	pmio_write(0x03, 0x4A);
-}
-#endif
-
-/*
-* Add any south bridge setting.
-*/
-static void sb800_pci_cfg(void)
-{
-	pci_devfn_t dev;
-	u8 byte;
-
-	/* SMBus Device, BDF:0-20-0 */
-	dev = PCI_DEV(0, 0x14, 0);
-	/* Enable watchdog decode timer */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= (1 << 3);
-	pci_write_config8(dev, 0x41, byte);
-
-	/* rpr 7.4. Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
-	 * generated PCIRST#. */
-	byte = pmio_read(0xF0);
-	byte |= (1 << 2);
-	pmio_write(0xF0, byte);
-
-	/* IDE Device, BDF:0-20-1 */
-	dev = PCI_DEV(0, 0x14, 1);
-	/* Enable IDE Explicit prefetch, 0x63[0] clear */
-	byte = pci_read_config8(dev, 0x63);
-	byte &= 0xfe;
-	pci_write_config8(dev, 0x63, byte);
-
-	/* LPC Device, BDF:0-20-3 */
-	/* The code below is ported from old chipset. It is not
-	 * Mentioned in RPR. But I keep them. The registers and the
-	 * comments are compatible. */
-	dev = PCI_DEV(0, 0x14, 3);
-	/* Enabling LPC DMA function. */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
-	/* Disabling LPC TimeOut. 0x48[7] clear. */
-	byte = pci_read_config8(dev, 0x48);
-	byte &= 0x7f;
-	pci_write_config8(dev, 0x48, byte);
-	/* Disabling LPC MSI Capability, 0x78[1] clear. */
-	byte = pci_read_config8(dev, 0x78);
-	byte &= 0xfd;
-	pci_write_config8(dev, 0x78, byte);
-
-	/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
-	dev = PCI_DEV(0, 0x11, 0);
-	/* rpr7.12 SATA MSI and D3 Power State Capability. */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x40, byte);
-	if (get_sb800_revision() <= 0x12)
-		pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */
-	else
-		pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */
-	byte &= ~(1 << 0);
-	pci_write_config8(dev, 0x40, byte);
-}
-
-/*
-*/
-static void sb800_por_init(void)
-{
-	/* sbDevicesPorInitTable + sbK8PorInitTable */
-	sb800_devices_por_init();
-
-	/* sbPmioPorInitTable + sbK8PmioPorInitTable */
-	//sb800_pmio_por_init();
-}
-
-/*
-* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
-*/
-static void sb800_before_pci_init(void)
-{
-	sb800_pci_cfg();
-}
-
-/*
-* This function should be called after enable_sb800_smbus().
-*/
-static void sb800_early_setup(void)
-{
-	printk(BIOS_INFO, "sb800_early_setup()\n");
-	sb800_por_init();
-	sb800_acpi_init();
-}
-
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
-{
-	int i;
-	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
-
-	for (i = 0; i < size; i++) {
-		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
-		nvram_pos++;
-	}
-
-	return nvram_pos;
-}
-
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
-{
-	u32 data = *old_dword;
-	int i;
-	for (i = 0; i < size; i++) {
-		outb(nvram_pos, BIOSRAM_INDEX);
-		data &= ~(0xff << (i * 8));
-		data |= inb(BIOSRAM_DATA) << (i *8);
-		nvram_pos++;
-	}
-	*old_dword = data;
-	printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size,
-		nvram_pos-size);
-	return nvram_pos;
-}
-
-#endif
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
deleted file mode 100644
index 2c193cbe4c..0000000000
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <device/mmio.h>
-#include <device/pci_ehci.h>
-#include <device/pci_def.h>
-#include "sb800.h"
-
-#define DEBUGPORT_MISC_CONTROL		0x80
-
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
-{
-	/* Enable all of the USB controllers */
-	outb(0xEF, PM_INDEX);
-	outb(0x7F, PM_DATA);
-
-	if (hcd_idx == 3)
-		return PCI_DEV(0, 0x16, 2);
-	else if (hcd_idx == 2)
-		return PCI_DEV(0, 0x13, 2);
-	else
-		return PCI_DEV(0, 0x12, 2);
-}
-
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
-{
-	u8 *base_regs = pci_ehci_base_regs(dev);
-	u32 reg32;
-
-	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
-	reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
-	reg32 &= ~(0xf << 28);
-	reg32 |= (port << 28);
-	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
-	write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
-}
diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c
deleted file mode 100644
index acda6dbd52..0000000000
--- a/src/southbridge/amd/sb800/fadt.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Raptor Engineering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <device/device.h>
-#include <cpu/amd/powernow.h>
-#include <version.h>
-
-#include "sb800.h"
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB800_ACPI_IO_BASE);
-
-	/* Prepare the header */
-	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(acpi_fadt_t);
-	header->revision = get_acpi_table_revision(FADT);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = asl_revision;
-
-	fadt->firmware_ctrl = (u32) facs;
-	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
-	fadt->preferred_pm_profile = 0x03;
-	fadt->sci_int = 9;
-	/* disable system management mode by setting to 0: */
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0xf0;
-	fadt->acpi_disable = 0xf1;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
-	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
-	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
-	fadt->gpe1_blk = 0x0000;	/* we don't have gpe1 block, do we? */
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 101;
-	fadt->p_lvl3_lat = 1001;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alarm work */
-	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
-	fadt->flags = 0x0001c1a5;/* 0x25; */
-
-	fadt->res2 = 0;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.access_size = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0x0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = (u32) facs;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (u32) dsdt;
-	fadt->x_dsdt_h = 0;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.access_size = 0;
-	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 4;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.access_size = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.access_size = 0;
-	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 2;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.access_size = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 0;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.access_size = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.access_size = 0;
-	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 32;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.access_size = 0;
-	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.access_size = 0;
-	fadt->x_gpe1_blk.addrl = 0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	if (CONFIG(CPU_AMD_MODEL_10XXX))
-		amd_powernow_update_fadt(fadt);
-
-	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
deleted file mode 100644
index 8cac15369d..0000000000
--- a/src/southbridge/amd/sb800/hda.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/mmio.h>
-#include <delay.h>
-#include "sb800.h"
-
-#define HDA_ICII_REG 0x68
-#define HDA_ICII_BUSY (1 << 0)
-#define HDA_ICII_VALID (1 << 1)
-
-static int set_bits(void *port, u32 mask, u32 val)
-{
-	u32 dword;
-	int count;
-
-	/* Write (val & ~mask) to port */
-	val &= mask;
-	dword = read32(port);
-	dword &= ~mask;
-	dword |= val;
-	write32(port, dword);
-
-	/* Wait for readback of register to
-	 * match what was just written to it
-	 */
-	count = 50;
-	do {
-		/* Wait 1ms based on BKDG wait time */
-		mdelay(1);
-		dword = read32(port);
-		dword &= mask;
-	} while ((dword != val) && --count);
-
-	/* Timeout occurred */
-	if (!count)
-		return -1;
-	return 0;
-}
-
-static u32 codec_detect(void *base)
-{
-	u32 dword;
-
-	/* Before Codec detection, we need to set the GPIO167-170 as
-	 * AZ_SDINx. */
-	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
-	if (set_bits(base + 0x08, 1, 0) == -1)
-		goto no_codec;
-
-	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	if (set_bits(base + 0x08, 1, 1) == -1)
-		goto no_codec;
-
-	/* Delay for 1 ms since the BKDG does */
-	mdelay(1);
-
-	/* Read in Codec location (BAR + 0xe)[3..0]*/
-	dword = read32(base + 0xe);
-	dword &= 0x0F;
-	if (!dword)
-		goto no_codec;
-
-	return dword;
-
-no_codec:
-	/* Codec Not found */
-	/* Put HDA back in reset (BAR + 0x8) [0] */
-	set_bits(base + 0x08, 1, 0);
-	printk(BIOS_DEBUG, "No codec!\n");
-	return 0;
-}
-
-/**
- *  Wait 50usec for the codec to indicate it is ready
- *  no response would imply that the codec is non-operative
- */
-static int wait_for_ready(void *base)
-{
-	/* Use a 50 usec timeout - the Linux kernel uses the
-	 * same duration */
-
-	int timeout = 50;
-
-	while (timeout--) {
-		u32 dword = read32(base +  HDA_ICII_REG);
-		if (!(dword & HDA_ICII_BUSY))
-			return 0;
-		udelay(1);
-	}
-
-	return -1;
-}
-
-/**
- *  Wait 50usec for the codec to indicate that it accepted
- *  the previous command.  No response would imply that the code
- *  is non-operative
- */
-static int wait_for_valid(void *base)
-{
-	/* Use a 50 usec timeout - the Linux kernel uses the
-	 * same duration */
-
-	int timeout = 50;
-	while (timeout--) {
-		u32 dword = read32(base + HDA_ICII_REG);
-		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
-			HDA_ICII_VALID)
-			return 0;
-		udelay(1);
-	}
-
-	return -1;
-}
-
-static void codec_init(void *base, int addr)
-{
-	u32 dword;
-
-	/* 1 */
-	if (wait_for_ready(base) == -1)
-		return;
-
-	dword = (addr << 28) | 0x000f0000;
-	write32(base + 0x60, dword);
-
-	if (wait_for_valid(base) == -1)
-		return;
-
-	dword = read32(base + 0x64);
-
-	/* 2 */
-	printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
-}
-
-static void codecs_init(void *base, u32 codec_mask)
-{
-	int i;
-	for (i = 3; i >= 0; i--) {
-		if (codec_mask & (1 << i))
-			codec_init(base, i);
-	}
-}
-
-static void hda_init(struct device *dev)
-{
-	u32 dword;
-	void *base;
-	struct resource *res;
-	u32 codec_mask;
-
-	/* Program the 2C to 0x437b1002 */
-	dword = 0x43831002;
-	pci_write_config32(dev, 0x2c, dword);
-
-	/* Read in BAR */
-	/* Is this right? HDA allows for a 64-bit BAR
-	 * but this is only setup for a 32-bit one
-	 */
-	res = find_resource(dev, 0x10);
-	if (!res)
-		return;
-
-	base = res2mmio(res, 0, 0);
-	printk(BIOS_DEBUG, "base = 0x%p\n", base);
-	codec_mask = codec_detect(base);
-
-	if (codec_mask) {
-		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
-		codecs_init(base, codec_mask);
-	}
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
-};
-
-static struct device_operations hda_audio_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = hda_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver hdaaudio_driver __pci_driver = {
-	.ops = &hda_audio_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_HDA,
-};
diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c
deleted file mode 100644
index 77e2f5ef1d..0000000000
--- a/src/southbridge/amd/sb800/ide.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "sb800.h"
-#include "chip.h"
-
-static void ide_init(struct device *dev)
-{
-	struct southbridge_amd_sb800_config *conf;
-	/* Enable ide devices so the linux ide driver will work */
-	u32 dword;
-	u8 byte;
-
-	conf = dev->chip_info;
-
-	/* RPR9.1 disable MSI */
-	/* TODO: For A14, it should set as 1. I doubt it. */
-	dword = pci_read_config32(dev, 0x70);
-	dword &= ~(1 << 16);
-	pci_write_config32(dev, 0x70, dword);
-
-	/* Ultra DMA mode */
-	/* enable UDMA */
-	byte = pci_read_config8(dev, 0x54);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x54, byte);
-
-	/* Enable I/O Access&& Bus Master */
-	dword = pci_read_config16(dev, 0x4);
-	dword |= 1 << 2;
-	pci_write_config16(dev, 0x4, dword);
-
-	/* set ide as primary, if you want to boot from IDE, you'd better set it
-	 * in mainboard/Config.lb */
-	if (conf->boot_switch_sata_ide == 1) {
-		byte = pci_read_config8(dev, 0xAD);
-		byte |= 1 << 4;
-		pci_write_config8(dev, 0xAD, byte);
-	}
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
-};
-
-static struct device_operations ide_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = ide_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
-	.ops = &ide_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_IDE,
-};
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
deleted file mode 100644
index 0ca50cce74..0000000000
--- a/src/southbridge/amd/sb800/lpc.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pnp.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/i8254.h>
-#include <pc80/i8259.h>
-#include <pc80/isa-dma.h>
-#include <arch/acpi.h>
-#include "sb800.h"
-
-static void lpc_init(struct device *dev)
-{
-	u8 byte;
-	u32 dword;
-	struct device *sm_dev;
-
-	/* Enable the LPC Controller */
-	sm_dev = pcidev_on_root(0x14, 0);
-	dword = pci_read_config32(sm_dev, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(sm_dev, 0x64, dword);
-
-	/* Initialize isa dma */
-	isa_dma_init();
-
-	/* Enable DMA transaction on the LPC bus */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
-
-	/* Disable the timeout mechanism on LPC */
-	byte = pci_read_config8(dev, 0x48);
-	byte &= ~(1 << 7);
-	pci_write_config8(dev, 0x48, byte);
-
-	/* Disable LPC MSI Capability */
-	byte = pci_read_config8(dev, 0x78);
-	byte &= ~(1 << 1);
-	byte &= ~(1 << 0);	/* Keep the old way. i.e., when bus master/DMA cycle is going
-				   on on LPC, it holds PCI grant, so no LPC slave cycle can
-				   interrupt and visit LPC. */
-	pci_write_config8(dev, 0x78, byte);
-
-	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
-	/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
-	byte = pci_read_config8(dev, 0xBB);
-	byte |= 1 << 0 | 1 << 3;
-	pci_write_config8(dev, 0xBB, byte);
-
-	cmos_check_update_date();
-
-	setup_i8259(); /* Initialize i8259 pic */
-	setup_i8254(); /* Initialize i8254 timers */
-}
-
-static void sb800_lpc_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
-
-	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
-
-	/* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->base = 0;
-	res->size = 0x1000;
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	//res = new_resource(dev, 3);
-	//res->base = IO_APIC_ADDR;
-	//res->size = 0x00001000;
-	//res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	compact_resources(dev);
-}
-
-static void sb800_lpc_set_resources(struct device *dev)
-{
-	struct resource *res;
-
-	pci_dev_set_resources(dev);
-
-	/* Special case. SPI Base Address. The SpiRomEnable should be set. */
-	res = find_resource(dev, 0xA0);
-	pci_write_config32(dev, 0xA0, res->base | 1 << 1);
-
-}
-
-/**
- * @brief Enable resources for children devices
- *
- * @param dev the device whose children's resources are to be enabled
- *
- */
-static void sb800_lpc_enable_childrens_resources(struct device *dev)
-{
-	struct bus *link;
-	u32 reg, reg_x;
-	int var_num = 0;
-	u16 reg_var[3] = {0x0, 0x0, 0x0};
-	u8 wiosize = pci_read_config8(dev, 0x74);
-
-	reg = pci_read_config32(dev, 0x44);
-	reg_x = pci_read_config32(dev, 0x48);
-
-	for (link = dev->link_list; link; link = link->next) {
-		struct device *child;
-		for (child = link->children; child;
-		     child = child->sibling) {
-			if (child->enabled
-			    && (child->path.type == DEVICE_PATH_PNP)) {
-				struct resource *res;
-				for (res = child->resource_list; res; res = res->next) {
-					u32 base, end;	/*  don't need long long */
-					if (!(res->flags & IORESOURCE_IO))
-						continue;
-					base = res->base;
-					end = resource_end(res);
-					printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n",
-					     dev_path(child), base, end);
-					switch (base) {
-					case 0x60:	/*  KB */
-					case 0x64:	/*  MS */
-						reg |= (1 << 29);
-						break;
-					case 0x3f8:	/*  COM1 */
-						reg |= (1 << 6);
-						break;
-					case 0x2f8:	/*  COM2 */
-						reg |= (1 << 7);
-						break;
-					case 0x378:	/*  Parallel 1 */
-						reg |= (1 << 0);
-						reg |= (1 << 1); /* + 0x778 for ECP */
-						break;
-					case 0x3f0:	/*  FD0 */
-						reg |= (1 << 26);
-						break;
-					case 0x220:	/*  Audio 0 */
-						reg |= (1 << 8);
-						break;
-					case 0x300:	/*  Midi 0 */
-						reg |= (1 << 18);
-						break;
-					case 0x400:
-						reg_x |= (1 << 16);
-						break;
-					case 0x480:
-						reg_x |= (1 << 17);
-						break;
-					case 0x500:
-						reg_x |= (1 << 18);
-						break;
-					case 0x580:
-						reg_x |= (1 << 19);
-						break;
-					case 0x4700:
-						reg_x |= (1 << 22);
-						break;
-					case 0xfd60:
-						reg_x |= (1 << 23);
-						break;
-					default:
-						if (var_num >= 3)
-							continue;	/* only 3 var ; compact them ? */
-						switch (var_num) {
-						case 0:
-							reg_x |= (1 << 2);
-							if ((end - base) < 16)
-								wiosize |= (1 << 0);
-							break;
-						case 1:
-							reg_x |= (1 << 24);
-							if ((end - base) < 16)
-								wiosize |= (1 << 2);
-							break;
-						case 2:
-							reg_x |= (1 << 25);
-							reg_x |= (1 << 24);
-							if ((end - base) < 16)
-								wiosize |= (1 << 3);
-							break;
-						}
-						reg_var[var_num++] =
-						    base & 0xffff;
-					}
-				}
-			}
-		}
-	}
-	pci_write_config32(dev, 0x44, reg);
-	pci_write_config32(dev, 0x48, reg_x);
-	/* Set WideIO for as many IOs found (fall through is on purpose) */
-	switch (var_num) {
-	case 3:
-		pci_write_config16(dev, 0x90, reg_var[2]);
-		/* fall through */
-	case 2:
-		pci_write_config16(dev, 0x66, reg_var[1]);
-		/* fall through */
-	case 1:
-		pci_write_config16(dev, 0x64, reg_var[0]);
-		break;
-	}
-	pci_write_config8(dev, 0x74, wiosize);
-}
-
-static void sb800_lpc_enable_resources(struct device *dev)
-{
-	pci_dev_enable_resources(dev);
-	sb800_lpc_enable_childrens_resources(dev);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
-};
-
-static struct device_operations lpc_ops = {
-	.read_resources = sb800_lpc_read_resources,
-	.set_resources = sb800_lpc_set_resources,
-	.enable_resources = sb800_lpc_enable_resources,
-#if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables      = acpi_write_hpet,
-#endif
-	.init = lpc_init,
-	.scan_bus = scan_static_bus,
-	.ops_pci = &lops_pci,
-};
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_LPC,
-};
diff --git a/src/southbridge/amd/sb800/pci.c b/src/southbridge/amd/sb800/pci.c
deleted file mode 100644
index 025d0a3643..0000000000
--- a/src/southbridge/amd/sb800/pci.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "sb800.h"
-
-static void pci_init(struct device *dev)
-{
-	u32 dword;
-	u8 byte;
-
-	/* RPR 6.1 Enables the PCI-bridge subtractive decode */
-	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4B, byte);
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
-
-	/* RPR6.2 PCI-bridge upstream dual address window */
-	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
-	byte = pci_read_config8(dev, 0x50);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x50, byte);
-
-	/* RPR 6.3 Enable One-Prefetch-Channel Mode */
-	dword = pci_read_config32(dev, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(dev, 0x64, dword);
-
-	/* rpr6.4 Adjusting CLKRUN# */
-	dword = pci_read_config32(dev, 0x64);
-	dword |= (1 << 15);
-	pci_write_config32(dev, 0x64, dword);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pci_init,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_PCI,
-};
diff --git a/src/southbridge/amd/sb800/pcie.c b/src/southbridge/amd/sb800/pcie.c
deleted file mode 100644
index d0c5260910..0000000000
--- a/src/southbridge/amd/sb800/pcie.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "sb800.h"
-
-static void pcie_init(struct device *dev)
-{
-	/* Enable pci error detecting */
-	u32 dword;
-
-	printk(BIOS_INFO, "pcie_init in rs780_ht.c\n");
-
-	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* System error enable */
-	dword |= (1 << 30);	/* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pcie_init,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pciea_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_PCIEA,
-};
-
-static const struct pci_driver pcieb_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_PCIEB,
-};
-static const struct pci_driver pciec_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_PCIEC,
-};
-static const struct pci_driver pcied_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_PCIED,
-};
diff --git a/src/southbridge/amd/sb800/ramtop.c b/src/southbridge/amd/sb800/ramtop.c
deleted file mode 100644
index 889c699379..0000000000
--- a/src/southbridge/amd/sb800/ramtop.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
-#include "sb800.h"
-
-int acpi_get_sleep_type(void)
-{
-	u16 tmp;
-	tmp = inw(ACPI_PM1_CNT_BLK);
-	return ((tmp & (7 << 10)) >> 10);
-}
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
-	u32 dword = ramtop;
-	int nvram_pos = 0xfc, i;
-	for (i = 0; i < 4; i++) {
-		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
-		nvram_pos++;
-	}
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
-	uint32_t xdata = 0;
-	int xnvram_pos = 0xfc, xi;
-	for (xi = 0; xi < 4; xi++) {
-		outb(xnvram_pos, BIOSRAM_INDEX);
-		xdata &= ~(0xff << (xi * 8));
-		xdata |= inb(BIOSRAM_DATA) << (xi *8);
-		xnvram_pos++;
-	}
-	return xdata;
-}
diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c
deleted file mode 100644
index bd578b6c0d..0000000000
--- a/src/southbridge/amd/sb800/reset.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <arch/io.h>
-#include <reset.h>
-
-#include <northbridge/amd/amdk8/reset_test.c>
-
-void do_board_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
deleted file mode 100644
index 8611272d78..0000000000
--- a/src/southbridge/amd/sb800/sata.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <delay.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <device/mmio.h>
-#include "sb800.h"
-#include "chip.h"
-
-static int sata_drive_detect(int portnum, u16 iobar)
-{
-	u8 byte, byte2;
-	int i = 0;
-	outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
-	while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
-		(byte != (0xA0 + 0x10 * (portnum % 2))) ||
-		((byte2 & 0x88) != 0)) {
-		printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
-		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
-			/* This will happen at the first iteration of this loop
-			 * if the first SATA port is unpopulated and the
-			 * second SATA port is populated.
-			 */
-			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
-				"retrying init\n", i * 10);
-			return 1;
-		} else
-			printk(BIOS_SPEW, "drive detection not yet completed, "
-				"waiting...\n");
-		mdelay(10);
-		i++;
-	}
-	printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
-	return 0;
-}
-
-static void sb800_setup_sata_phys(struct device *dev)
-{
-	int i;
-	static const u32 sata_phy[][3] = {
-		{0x0056A607, 0x00061400, 0x00061302}, /* port 0 */
-		{0x0056A607, 0x00061400, 0x00061302}, /* port 1 */
-		{0x0056A607, 0x00061402, 0x00064300}, /* port 2 */
-		{0x0056A607, 0x00061402, 0x00064300}, /* port 3 */
-		{0x0056A700, 0x00061502, 0x00064302}, /* port 4 */
-		{0x0056A700, 0x00061502, 0x00064302}  /* port 5 */
-	};
-	/* RPR8.4 */
-	/* Port 0 - 5 */
-	for (i = 0; i < 6; i++) {
-		pci_write_config16(dev, 0x84, 0x3006 | i << 9);
-		pci_write_config32(dev, 0x94, sata_phy[i][0]); /* Gen 3 */
-		pci_write_config16(dev, 0x84, 0x2006 | i << 9);
-		pci_write_config32(dev, 0x94, sata_phy[i][1]); /* Gen 2 */
-		pci_write_config16(dev, 0x84, 0x1006 | i << 9);
-		pci_write_config32(dev, 0x94, sata_phy[i][2]); /* Gen 1 */
-	}
-
-}
-static void sata_init(struct device *dev)
-{
-	u8 byte;
-	u16 word;
-	u32 dword;
-	u8 rev_id;
-	void *sata_bar5;
-	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
-	int i, j;
-
-	struct southbridge_ati_sb800_config *conf;
-	conf = dev->chip_info;
-
-	struct device *sm_dev;
-	/* SATA SMBus Disable */
-	sm_dev = pcidev_on_root(0x14, 0);
-
-	/* get rev_id */
-	rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F;
-
-	/* get base address */
-	sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
-	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
-	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
-	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
-	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
-	sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
-
-	printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
-	printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
-	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
-	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
-	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5);	/* e0309000 */
-
-	/* SERR-Enable */
-	word = pci_read_config16(dev, 0x04);
-	word |= (1 << 8);
-	pci_write_config16(dev, 0x04, word);
-
-	/* Set SATA Operation Mode, Set to IDE mode */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 0);
-	//byte |= (1 << 4);
-	pci_write_config8(dev, 0x40, byte);
-
-	dword = 0x01018f00;
-	pci_write_config32(dev, 0x8, dword);
-
-	/* Program the 2C to 0x43801002 */
-	dword = 0x43801002;
-	pci_write_config32(dev, 0x2c, dword);
-
-	pci_write_config8(dev, 0x34, 0x70); /* 8.11 SATA MSI and D3 Power State Capability */
-
-	dword = read32(sata_bar5 + 0xFC);
-	dword &= ~(1 << 11);	/* rpr 8.8. Disabling Aggressive Link Power Management */
-	dword &= ~(1 << 12);	/* rpr 8.9.1 Disabling Port Multiplier support. */
-	dword &= ~(1 << 10);	/* rpr 8.9.2 disabling FIS-based Switching support */
-	dword &= ~(1 << 19);	/* rpr 8.10. Disabling CCC (Command Completion Coalescing) Support */
-	write32((sata_bar5 + 0xFC), dword);
-
-	dword = read32(sata_bar5 + 0xF8);
-	dword &= ~(0x3F << 22);	/* rpr 8.9.2 disabling FIS-based Switching support */
-	write32(sata_bar5 + 0xF8, dword);
-
-	byte = pci_read_config8(dev, 0x40);
-	byte &= ~(1 << 0);
-	pci_write_config8(dev, 0x40, byte);
-
-	/* rpr 8.3 */
-	printk(BIOS_SPEW, "rev_id=%x\n", rev_id);
-	dword = pci_read_config32(dev, 0x84);
-	if (rev_id == 0x11)	/* A11 */
-		dword |= 1 << 22;
-	pci_write_config32(dev, 0x84, dword);
-
-	/* rpr8.12 Program the watchdog counter to 0x20 */
-	byte = pci_read_config8(dev, 0x44);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x44, byte);
-
-	pci_write_config8(dev, 0x46, 0x20);
-
-	sb800_setup_sata_phys(dev);
-	/* Enable the I/O, MM, BusMaster access for SATA */
-	byte = pci_read_config8(dev, 0x4);
-	byte |= 7 << 0;
-	pci_write_config8(dev, 0x4, byte);
-
-	/* RPR7.7 SATA drive detection. */
-	/* Use BAR5+0x128,BAR0 for Primary Slave */
-	/* Use BAR5+0x1A8,BAR0 for Primary Slave */
-	/* Use BAR5+0x228,BAR2 for Secondary Master */
-	/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
-	/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */
-	/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
-
-	/* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
-
-	for (i = 0; i < 4; i++) {
-		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
-		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
-		byte &= 0xF;
-		if (byte == 0x1) {
-			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
-			/* Try to do something about it. */
-			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
-
-			/* Read in Port-N Serial ATA Control Register */
-			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
-
-			/* Set Reset Bit and 1.5g bit */
-			byte |= 0x11;
-			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
-
-			/* Wait 1ms */
-			mdelay(1);
-
-			/* Clear Reset Bit */
-			byte &= ~0x01;
-			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
-
-			/* Wait 1ms */
-			mdelay(1);
-
-			/* Reread status */
-			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
-			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
-			byte &= 0xF;
-		}
-
-		if (byte == 0x3) {
-			for (j = 0; j < 10; j++) {
-				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
-					break;
-			}
-			printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
-					(i / 2) ? "Secondary" : "Primary",
-					(i % 2) ? "Slave" : "Master",
-					(j == 10) ? "not " : "",
-					(j == 10) ? j : j + 1);
-		} else {
-			printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
-					(i / 2) ? "Secondary" : "Primary",
-					(i % 2) ? "Slave" : "Master", i);
-		}
-	}
-
-	/* Below is CIM InitSataLateFar */
-	/* Enable interrupts from the HBA  */
-	byte = read8(sata_bar5 + 0x4);
-	byte |= 1 << 1;
-	write8((sata_bar5 + 0x4), byte);
-
-	/* Clear error status */
-	write32((sata_bar5 + 0x130), 0xFFFFFFFF);
-	write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
-	write32((sata_bar5 + 0x230), 0xFFFFFFFF);
-	write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
-	write32((sata_bar5 + 0x330), 0xFFFFFFFF);
-	write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
-
-	/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
-	/* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */
-
-	/* word = 0x0000; */
-	/* word = pm_ioread(0x28); */
-	/* byte = pm_ioread(0x29); */
-	/* word |= byte<<8; */
-	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
-	/* write32(word, 0x80000000); */
-}
-
-static struct pci_operations lops_pci = {
-	/* .set_subsystem = pci_dev_set_subsystem, */
-};
-
-static struct device_operations sata_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = sata_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver sata0_driver __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_SATA,
-};
diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c
deleted file mode 100644
index c7efaec732..0000000000
--- a/src/southbridge/amd/sb800/sb800.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-
-#include <arch/io.h>
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "sb800.h"
-#include "smbus.h"
-#include "chip.h"
-
-static struct device *find_sm_dev(struct device *dev, u32 devfn)
-{
-	struct device *sm_dev;
-
-	sm_dev = pcidev_path_behind(dev->bus, devfn);
-	if (!sm_dev)
-		return sm_dev;
-
-	if ((sm_dev->vendor != PCI_VENDOR_ID_ATI) ||
-	    ((sm_dev->device != PCI_DEVICE_ID_ATI_SB800_SM))) {
-		u32 id;
-		id = pci_read_config32(sm_dev, PCI_VENDOR_ID);
-		if ((id !=
-		     (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_SB800_SM << 16))))
-		{
-			sm_dev = 0;
-		}
-	}
-
-	return sm_dev;
-}
-
-void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)
-{
-	u32 reg_old, reg;
-	reg = reg_old = pci_read_config32(sm_dev, reg_pos);
-	reg &= ~mask;
-	reg |= val;
-	if (reg != reg_old) {
-		pci_write_config32(sm_dev, reg_pos, reg);
-	}
-}
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
-	outb(reg, port_base);
-	outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
-	outb(reg, port_base);
-	return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
-	return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
-	return pmio_read_index(PM2_INDEX, reg);
-}
-
-static void set_pmio_enable_bits(u32 reg_pos, u32 mask, u32 val)
-{
-	u8 reg_old, reg;
-	reg = reg_old = pm_ioread(reg_pos);
-	reg &= ~mask;
-	reg |= val;
-	if (reg != reg_old) {
-		pm_iowrite(reg_pos, reg);
-	}
-}
-
-u16 tx_convert_table[] = {
-	[0x0] = 0xFFFF,
-	[0x1] = 0xFFFE,
-	[0x2] = 0xFFFC,
-	[0x3] = 0xFFF8,
-	[0x4] = 0xFFF0,
-	[0x5] = 0xFFE0,
-	[0x6] = 0xFFC0,
-	[0x7] = 0xFF80,
-	[0x8] = 0xFF00,
-	[0x9] = 0xFE00,
-	[0xA] = 0xFC00,
-	[0xB] = 0xF800,
-	[0xC] = 0xF000,
-	[0xD] = 0xE000,
-	[0xE] = 0xC000,
-	[0xF] = 0x8000
-};
-
-u16 rx_convert_table[] = {
-	[0x0] = 0x0001,
-	[0x1] = 0x0003,
-	[0x2] = 0x0007,
-	[0x3] = 0x000F,
-	[0x4] = 0x001F,
-	[0x5] = 0x003F,
-	[0x6] = 0x007F,
-	[0x7] = 0x00FF,
-	[0x8] = 0x01FF,
-	[0x9] = 0x03FF,
-	[0xA] = 0x07FF,
-	[0xB] = 0x0FFF,
-	[0xC] = 0x1FFF,
-	[0xD] = 0x3FFF,
-	[0xE] = 0x7FFF,
-	[0xF] = 0xFFFF
-};
-
-/* PCIe General Purpose Ports */
-/* v:1814, d:3090. cp421A */
-static void set_sb800_gpp(struct device *dev)
-{
-	struct southbridge_amd_sb800_config *conf;
-	u32 imp_rb, lc_status;
-	u8 port;
-
-	conf = dev->chip_info;
-	port = dev->path.pci.devfn & 3;
-
-	/* 5.1 GPP Lane Configuration */
-	/* To support one of 4 legal configurations:
-	 * 0000: PortA lanes[3:0]
-	 * 0001: N/A
-	 * 0010: PortA lanes[1:0], PortB lanes[3:2]
-	 * 0011: PortA lanes[1:0], PortB lane2, PortC lane3
-	 * 0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
-	 * Other combinations are not supported.
-	 */
-	/* CIMx: Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function */
-	abcfg_reg(0x90, 1 << 20, 1 << 20);
-
-	printk(BIOS_DEBUG, "set_sb800_gpp() 1\n");
-	//abcfg_reg(0xC0, 0xF << 0, 0x4 << 0); /* bimini:4; tarpon:3 */
-	abcfg_reg(0xC0, 0xF << 0, (conf->gpp_configuration & 0xF) << 0); /* bimini:4; tarpon:3 */
-
-	printk(BIOS_DEBUG, "set_sb800_gpp() 2,\n");
-	/* 5.2 Enabling GPP Port A/B/C/D */
-	//abcfg_reg(0xC0, 0xF << 4, 0x1 << 4);
-	abcfg_reg(0xC0, 0xF << 4, dev->enabled ? 0x1 << (4 + port) : 0);
-
-	printk(BIOS_DEBUG, "set_sb800_gpp() 3\n");
-	/* 5.3 Releasing GPP Reset */
-	abcfg_reg(0xC0, 0x1 << 8, 0x0 << 8);
-
-	/* release training */
-	abcfg_reg(0xC0, 0xF << 12, 0x0 << 12);
-	/* 5.4 Power Saving Feature for GPP Lanes. Skip */
-	/* 5.5 PCIe Ports De-emphasis Settings. Skip */
-	abcfg_reg(0x340, 1 << 21, 0 << 21);
-	abcfg_reg(0x344, 1 << 21, 0 << 21);
-	abcfg_reg(0x348, 1 << 21, 0 << 21);
-	abcfg_reg(0x34C, 1 << 21, 0 << 21);
-	/* 5.6 PCIe PHY Calibration Impedance Value Setting */
-	/* AXINDC_Reg 0x60: TX_IMP_RB */
-	outl(0x30, 0xCD8);
-	outl(0x60, 0xCDC);
-	outl(0x34, 0xCD8);
-	imp_rb = inl(0xCDC);
-
-	printk(BIOS_DEBUG, "imp_rb 1=%x\n", imp_rb);
-	/* tx */
-	abcfg_reg(0xA4, 0x1FFF, (rx_convert_table[(imp_rb>>8)&0xF]) & 0x1FFF);
-	abcfg_reg(0xA4, 0x1FFF<<19, ((tx_convert_table[(imp_rb>>4)&0xF] >> 3) & 0x1FFF) << 19);
-
-	/* 5.4. */
-	abcfg_reg(0xA0, 3 << 12, 3 << 12);
-
-	axindxp_reg(0xa0, 0xf<<4, 3<<4);
-	rcindxp_reg(0xA0, 0, 0xF << 4, 1 << 0);
-	rcindxp_reg(0xA0, 1, 0xF << 4, 1 << 0);
-	rcindxp_reg(0xA0, 2, 0xF << 4, 1 << 0);
-	rcindxp_reg(0xA0, 3, 0xF << 4, 1 << 0);
-
-	/* 5.8 Disabling Serial Number Capability */
-	abcfg_reg(0x330, 1 << 26, 0 << 26);
-
-	abcfg_reg(0x50, 0xFFFFFFFF, 0x04000004);
-	abcfg_reg(0x54, 0xFFFFFFFF, 0x00040000);
-	abcfg_reg(0x80, 0xFFFFFFFF, 0x03060001);
-	abcfg_reg(0x90, 0xFFFFFFFF, 0x00300000);
-	abcfg_reg(0x98, 0xFFFFFFFF, 0x03034700);
-
-	pci_write_config32(dev, 0x80, 0x00000006);
-	/* Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 */
-	rcindxp_reg(0x70, 0, 1 << 19, 1 << 19);
-	//outl(3<<29|0<<24|0x70, 0xCD8);
-	/* Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 */
-	rcindxp_reg(0x20, 0, 1 << 19, 0 << 19);
-	printk(BIOS_DEBUG, "imp_rb 5=%x\n", imp_rb);
-	outl(3<<29|0<<24|0xA5, 0xCD8);
-	lc_status = inl(0xCDC);
-	printk(BIOS_DEBUG, "lc_status=%x\n", lc_status);
-}
-
-void sb800_enable(struct device *dev)
-{
-	struct device *sm_dev = NULL;
-	struct device *bus_dev = NULL;
-	int index;
-	u32 deviceid;
-	u32 vendorid;
-
-	/* struct southbridge_ati_sb800_config *conf; */
-	/* conf = dev->chip_info; */
-	int i;
-
-	u32 devfn, dword;
-
-	printk(BIOS_DEBUG, "sb800_enable()\n");
-
-	/*
-	 *	0:11.0  SATA		bit 8 of pmio 0xDA : 1 - enable
-	 *	0:12.0  OHCI-USB1	bit 0 of pmio 0xEF
-	 *	0:12.2  EHCI-USB1	bit 1 of pmio 0xEF
-	 *	0:13.0  OHCI-USB2	bit 2 of pmio 0xEF
-	 *	0:13.2  EHCI-USB2	bit 3 of pmio 0xEF
-	 *	0:16.1  OHCI-USB3	bit 4 of pmio 0xEF
-	 *	0:16.2  EHCI-USB3	bit 5 of pmio 0xEF
-	 *	0:14.5  OHCI-USB4	bit 6 of pmio 0xEF
-	 *	0:14.0  SMBUS							0
-	 *	0:14.1  IDE							1
-	 *	0:14.2  HDA	bit 0 of pm_io 0xEB : 1 - enable
-	 *	0:14.3  LPC	bit 0 of pm_io 0xEC : 1 - enable
-	 *	0:14.4  PCI	bit 0 of pm_io 0xEA : 0 - enable
-	 *	0:14.6  GEC	bit 0 of pm_io 0xF6 : 0 - enable
-	 */
-	if (dev->device == 0x0000) {
-		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
-		deviceid = (vendorid >> 16) & 0xffff;
-		vendorid &= 0xffff;
-	} else {
-		vendorid = dev->vendor;
-		deviceid = dev->device;
-	}
-	bus_dev = dev->bus->dev;
-	if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) &&
-	    (bus_dev->device == PCI_DEVICE_ID_ATI_SB800_PCI)) {
-		devfn = (bus_dev->path.pci.devfn) & ~7;
-		sm_dev = find_sm_dev(bus_dev, devfn);
-		if (!sm_dev)
-			return;
-
-		/* something under 00:01.0 */
-		switch (dev->path.pci.devfn) {
-		case 5 << 3:
-			;
-		}
-
-		return;
-	}
-	printk(BIOS_DEBUG, "sb800_enable() 1\n");
-
-	i = (dev->path.pci.devfn) & ~7;
-	i += (3 << 3);
-	for (devfn = (0x14 << 3); devfn <= i; devfn += (1 << 3)) {
-		sm_dev = find_sm_dev(dev, devfn);
-		if (sm_dev)
-			break;
-	}
-	if (!sm_dev)
-		return;
-	printk(BIOS_DEBUG, "sb800_enable() 2\n");
-
-	switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) {
-	case PCI_DEVFN(0x11, 0):
-		index = 0;
-		set_pmio_enable_bits(0xDA, 1 << index,
-				     (dev->enabled ? 1 : 0) << index);
-		/* Set the device ID of SATA as 0x4390 to reduce the confusing. */
-		dword = pci_read_config32(dev, 0x40);
-		dword |= 1 << 0;
-		pci_write_config32(dev, 0x40, dword);
-		pci_write_config16(dev, 0x2, 0x4390);
-		dword &= ~1;
-		pci_write_config32(dev, 0x40, dword);//for (;;);
-		break;
-	case PCI_DEVFN(0x12, 0):
-	case PCI_DEVFN(0x12, 2):
-		index = (dev->path.pci.devfn & 0x3) / 2;
-		set_pmio_enable_bits(0xEF, 1 << index,
-				     (dev->enabled ? 1 : 0) << index);
-		break;
-	case PCI_DEVFN(0x13, 0):
-	case PCI_DEVFN(0x13, 2):
-		index = (dev->path.pci.devfn & 0x3) / 2 + 2;
-		set_pmio_enable_bits(0xEF, 1 << index,
-				     (dev->enabled ? 1 : 0) << index);
-		break;
-	case PCI_DEVFN(0x14, 0):
-		break;
-	case PCI_DEVFN(0x14, 1):
-		index = 3;
-		set_pmio_enable_bits(0xDA, 1 << index,
-				     (dev->enabled ? 0 : 1) << index);
-		break;
-	case PCI_DEVFN(0x14, 2):
-		index = 0;
-		set_pmio_enable_bits(0xEB, 1 << index,
-				     (dev->enabled ? 1 : 0) << index);
-		break;
-	case PCI_DEVFN(0x14, 3):
-		index = 0;
-		set_pmio_enable_bits(0xEC, 1 << index,
-				     (dev->enabled ? 1 : 0) << index);
-		break;
-	case PCI_DEVFN(0x14, 4):
-		index = 0;
-		set_pmio_enable_bits(0xEA, 1 << index,
-				     (dev->enabled ? 0 : 1) << index);
-		break;
-	case PCI_DEVFN(0x14, 5):
-		index = 6;
-		set_pmio_enable_bits(0xEF, 1 << index,
-				     (dev->enabled ? 1 : 0) << index);
-		break;
-	case PCI_DEVFN(0x14, 6):
-		index = 0;
-		set_pmio_enable_bits(0xF6, 1 << index,
-				     (dev->enabled ? 0 : 1) << index);
-		break;
-	case PCI_DEVFN(0x15, 0):
-		set_sb800_gpp(dev);
-		break;
-	case PCI_DEVFN(0x15, 1):
-	case PCI_DEVFN(0x15, 2):
-	case PCI_DEVFN(0x15, 3):
-		break;
-	case PCI_DEVFN(0x16, 0):
-	case PCI_DEVFN(0x16, 2):
-		index = (dev->path.pci.devfn & 0x3) / 2 + 4;
-		set_pmio_enable_bits(0xEF, 1 << index,
-				     (dev->enabled ? 1 : 0) << index);
-		break;
-	default:
-		printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev),
-			     deviceid);
-	}
-}
-
-struct chip_operations southbridge_amd_sb800_ops = {
-	CHIP_NAME("ATI SB800")
-	.enable_dev = sb800_enable,
-};
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
deleted file mode 100644
index 07c78ec429..0000000000
--- a/src/southbridge/amd/sb800/sb800.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef SB800_H
-#define SB800_H
-
-#include <types.h>
-#include <device/device.h>
-
-/* Power management index/data registers */
-#define BIOSRAM_INDEX	0xcd4
-#define BIOSRAM_DATA	0xcd5
-#define PM_INDEX	0xcd6
-#define PM_DATA		0xcd7
-#define PM2_INDEX	0xcd0
-#define PM2_DATA	0xcd1
-
-#define SB800_ACPI_IO_BASE 0x800
-
-#define ACPI_PM_EVT_BLK		(SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK	(SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK	(SB800_ACPI_IO_BASE + 0x17) /* 1 byte */
-#define ACPI_PM_TMR_BLK		(SB800_ACPI_IO_BASE + 0x20) /* 4 bytes */
-#define ACPI_GPE0_BLK		(SB800_ACPI_IO_BASE + 0x18) /* 8 bytes */
-#define ACPI_CPU_CONTROL	(SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */
-#define ACPI_CPU_P_LVL2		(ACPI_CPU_CONTROL + 0x4)    /* 1 byte */
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
-
-#define REV_SB800_A11	0x11
-#define REV_SB800_A12	0x12
-
-void sb800_lpc_port80(void);
-void sb800_pci_port80(void);
-void sb800_clk_output_48Mhz(void);
-
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-
-void sb800_enable(struct device *dev);
-
-#endif /* SB800_H */
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
deleted file mode 100644
index e1cf05ce09..0000000000
--- a/src/southbridge/amd/sb800/sm.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/smbus.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/ioapic.h>
-
-#include "sb800.h"
-#include "smbus.c"
-
-#define NMI_OFF 0
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-
-#define BIT0	(1 << 0)
-#define BIT1	(1 << 1)
-#define BIT2	(1 << 2)
-#define BIT3	(1 << 3)
-#define BIT4	(1 << 4)
-#define BIT5	(1 << 5)
-#define BIT6	(1 << 6)
-#define BIT7	(1 << 7)
-
-#define BIT8	(1 << 8)
-#define BIT9	(1 << 9)
-#define BIT10	(1 << 10)
-#define BIT11	(1 << 11)
-#define BIT12	(1 << 12)
-#define BIT13	(1 << 13)
-#define BIT14	(1 << 14)
-#define BIT15	(1 << 15)
-
-#define BIT16	(1 << 16)
-#define BIT17	(1 << 17)
-#define BIT18	(1 << 18)
-#define BIT19	(1 << 19)
-#define BIT20	(1 << 20)
-#define BIT21	(1 << 21)
-#define BIT22	(1 << 22)
-#define BIT23	(1 << 23)
-#define BIT24	(1 << 24)
-#define BIT25	(1 << 25)
-#define BIT26	(1 << 26)
-#define BIT27	(1 << 27)
-#define BIT28	(1 << 28)
-#define BIT29	(1 << 29)
-#define BIT30	(1 << 30)
-#define BIT31	(1 << 31)
-
-/*
-* SB800 enables all USB controllers by default in SMBUS Control.
-* SB800 enables SATA by default in SMBUS Control.
-*/
-
-static void sm_init(struct device *dev)
-{
-	u8 byte;
-
-	printk(BIOS_INFO, "sm_init().\n");
-
-	/* Don't rename APIC ID */
-	/* TODO: We should call setup_ioapic() here. But kernel hangs if CPU is K8.
-	 * We need to check out why and change back. */
-	clear_ioapic(VIO_APIC_VADDR);
-	//setup_ioapic(IO_APIC_ADDR, 0);
-
-	/* enable serial irq */
-	byte = pm_ioread(0x54);
-	byte |= 1 << 7;		/* enable serial irq function */
-	byte &= ~(0xF << 2);
-	byte |= 4 << 2;		/* set NumSerIrqBits=4 */
-	pm_iowrite(0x54, byte);
-
-	pm_iowrite(0x00, 0x0E);
-	pm_iowrite(0x0B, 0x02);
-	/* 2.11 IO Trap Settings */
-	abcfg_reg(0x10090, 1 << 16, 1 << 16);
-
-	/* 4.1 ab index */
-	//pci_write_config32(dev, 0xF0, AB_INDX);
-	pm_iowrite(0xE0, AB_INDX & 0xFF);
-	pm_iowrite(0xE1, (AB_INDX >> 8) & 0xFF);
-	pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF);
-	pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF);
-	/* Initialize the real time clock */
-	cmos_init(0);
-
-	byte = pm_ioread(0x8);
-	byte |= 1 << 2 | 1 << 4;
-	pm_iowrite(0x08, byte);
-	byte = pm_ioread(0x9);
-	byte |= 1 << 0;
-	pm_iowrite(0x09, byte);
-
-	abcfg_reg(0x10060, (BIT31), BIT31);
-	abcfg_reg(0x1009C, (BIT4 + BIT5), BIT4 + BIT5);
-	abcfg_reg(0x9C,    (BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7), BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7);
-	abcfg_reg(0x90,    (BIT21 + BIT22 + BIT23), BIT21 + BIT22 + BIT23);
-	abcfg_reg(0xF0,    (BIT6 + BIT5), BIT6 + BIT5);
-	abcfg_reg(0x10090, (BIT9 + BIT10 + BIT11 + BIT12), BIT9 + BIT10 + BIT11 + BIT12);
-	abcfg_reg(0x58,    (BIT10), BIT10);
-	abcfg_reg(0xF0,    (BIT3 + BIT4), BIT3 + BIT4);
-	abcfg_reg(0x54,    (BIT1), BIT1);
-	//
-	axindxc_reg(0x02, BIT9, BIT9);
-	axindxc_reg(0x10, BIT9, BIT9);
-
-	/* 4.2 Enabling Upstream DMA Access */
-	axcfg_reg(0x04, 1 << 2, 1 << 2);
-	/* 4.3 Enabling PCIB Prefetch Settings */
-	abcfg_reg(0x10060, 1 << 20, 1 << 20);
-	abcfg_reg(0x10064, 1 << 20, 1 << 20);
-
-	/* 4.4 Enabling OHCI Prefetch for Performance Enhancement, A12 */
-	abcfg_reg(0x80, 1 << 0, 1<< 0);
-
-	/* 4.5 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
-	/* 4.6 Enabling Additional Address Bits Checking in Downstream */
-	abcfg_reg(0x9c, 1 << 0, 1 << 0);
-	//abcfg_reg(0x9c, 3 << 0, 3 << 0); //A11
-
-	/* 4.7 Set B-Link Prefetch Mode */
-	abcfg_reg(0x80, 3 << 17, 3 << 17);
-
-	// RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]
-	// RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17]
-	abcfg_reg(0x90, 1 << 17 | 1 << 21, 1 << 17 | 1 << 21);
-	/* 4.8 Enabling Detection of Upstream Interrupts */
-	abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);
-
-	/* 4.9: Enabling Downstream Posted Transactions to Pass Non-Posted
-	 *  Transactions for the K8 Platform (for All Revisions) */
-	abcfg_reg(0x10090, 1 << 8, 1 << 8);
-
-	/* 4.10:Programming Cycle Delay for AB and BIF Clock Gating */
-	/* 4.11:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
-	abcfg_reg(0x10054, 0xFFFF0000, 0x01040000);
-	abcfg_reg(0x54, 0xFF << 16, 4 << 16);
-	abcfg_reg(0x54, 1 << 24, 0 << 24);
-	abcfg_reg(0x54, 1 << 26, 1 << 26);
-	abcfg_reg(0x98, 0xFFFFFF00, 0x00004700);
-
-	/* 4.12: Enabling AB and BIF Clock Gating */
-	abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
-
-	/* 4.13:Enabling Requester ID for upstream traffic. */
-	abcfg_reg(0x98, 3 << 16, 3 << 16);
-
-	abcfg_reg(0x50, 1 << 2, 0 << 2);
-
-	/* 5.2 Enabling GPP Port A/B/C/D */
-	//abcfg_reg(0xC0, 0xF << 4, 0xF << 4);
-
-	/* Enable SCI as irq9. */
-	outb(0x10, 0xC00);
-	outb(0x9, 0xC01);
-	/* Enabled IRQ input */
-	outb(0x9, 0xC00);
-	outb(0xF7, 0xC01);
-
-	abcfg_reg(0x90, 0xFFFFFFFF, 0x00F80040);
-	abcfg_reg(0xA0, 0xFFFFFFFF, 0x00000000);
-	abcfg_reg(0xA4, 0xFFFFFFFF, 0x00000000);
-	abcfg_reg(0xC0, 0xFFFFFFFF, 0x0000F014);
-	abcfg_reg(0x98, 0xFFFFFFFF, 0X01034700);
-}
-
-static int lsmbus_recv_byte(struct device *dev)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_recv_byte(res->base, device);
-}
-
-static int lsmbus_send_byte(struct device *dev, u8 val)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_send_byte(res->base, device, val);
-}
-
-static int lsmbus_read_byte(struct device *dev, u8 address)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_read_byte(res->base, device, address);
-}
-
-static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
-{
-	u32 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-
-	res = find_resource(pbus->dev, 0x90);
-
-	return do_smbus_write_byte(res->base, device, address, val);
-}
-static struct smbus_bus_operations lops_smbus_bus = {
-	.recv_byte = lsmbus_recv_byte,
-	.send_byte = lsmbus_send_byte,
-	.read_byte = lsmbus_read_byte,
-	.write_byte = lsmbus_write_byte,
-};
-
-static void sb800_sm_read_resources(struct device *dev)
-{
-	struct resource *res;
-	u8 byte;
-
-	/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
-	byte = pm_ioread(0x55);
-	byte |= 1 << 7;
-	pm_iowrite(0x55, byte);
-
-	/* Get the normal pci resources of this device */
-	/* pci_dev_read_resources(dev); */
-
-	byte = pm_ioread(0x55);
-	byte &= ~(1 << 7);
-	pm_iowrite(0x55, byte);
-
-	/* apic */
-	res = new_resource(dev, 0x74);
-	res->base  = IO_APIC_ADDR;
-	res->size = 256 * 0x10;
-	res->limit = 0xFEFFFFFUL;	/* res->base + res->size -1; */
-	res->align = 8;
-	res->gran = 8;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
-
-	#if 0			       /* Linux ACPI crashes when it is 1. For late debugging. */
-	res = new_resource(dev, 0x14); /* TODO: hpet */
-	res->base  = 0xfed00000;	/* reset hpet to widely accepted address */
-	res->size = 0x400;
-	res->limit = 0xFFFFFFFFUL;	/* res->base + res->size -1; */
-	res->align = 8;
-	res->gran = 8;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
-	#endif
-	/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
-
-	/* smbus */
-	//res = new_resource(dev, 0x90);
-	//res->base  = 0xB00;
-	//res->size = 0x10;
-	//res->limit = 0xFFFFUL;	/* res->base + res->size -1; */
-	//res->align = 8;
-	//res->gran = 8;
-	//res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
-
-
-	compact_resources(dev);
-}
-
-static void sb800_sm_set_resources(struct device *dev)
-{
-	struct resource *res;
-	u8 byte;
-
-	pci_dev_set_resources(dev);
-
-
-	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
-	byte = pm_ioread(0x52);
-	byte |= 1 << 6;
-	pm_iowrite(0x52, byte);
-
-	res = find_resource(dev, 0x74);
-
-	printk(BIOS_INFO, "sb800_sm_set_resources, res->base=0x%llx\n", res->base);
-
-	//pci_write_config32(dev, 0x74, res->base | 1 << 3);
-	pm_iowrite(0x34, res->base | 0x7);
-	pm_iowrite(0x35, (res->base >> 8) & 0xFF);
-	pm_iowrite(0x36, (res->base >> 16) & 0xFF);
-	pm_iowrite(0x37, (res->base >> 24) & 0xFF);
-#if 0				/* TODO:hpet */
-	res = find_resource(dev, 0x14);
-	pci_write_config32(dev, 0x14, res->base);
-#endif
-	//res = find_resource(dev, 0x90);
-	//pci_write_config32(dev, 0x90, res->base | 1);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
-};
-static struct device_operations smbus_ops = {
-	.read_resources = sb800_sm_read_resources,
-	.set_resources = sb800_sm_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = sm_init,
-	.scan_bus = scan_smbus,
-	.ops_pci = &lops_pci,
-	.ops_smbus_bus = &lops_smbus_bus,
-};
-static const struct pci_driver smbus_driver __pci_driver = {
-	.ops = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_SM,
-};
diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c
deleted file mode 100644
index fef6ab80c1..0000000000
--- a/src/southbridge/amd/sb800/smbus.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SB800_SMBUS_C_
-#define _SB800_SMBUS_C_
-
-#include <arch/io.h>
-#include "smbus.h"
-
-static int smbus_wait_until_ready(u32 smbus_io_base)
-{
-	u32 loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;
-		if (val == 0) {	/* ready now */
-			return 0;
-		}
-		outb(val, smbus_io_base + SMBHSTSTAT);
-	} while (--loops);
-	return -2;		/* time out */
-}
-
-static int smbus_wait_until_done(u32 smbus_io_base)
-{
-	u32 loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;	/* mask off reserved bits */
-		if (val & 0x1c) {
-			return -5;	/* error */
-		}
-		if (val == 0x02) {
-			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
-			return 0;
-		}
-	} while (--loops);
-	return -3;		/* timeout */
-}
-
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTCMD);
-
-	return byte;
-}
-
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the command... */
-	outb(val, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	return 0;
-}
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device,
-			      u32 address)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-
-	return byte;
-}
-
-int do_smbus_write_byte(u32 smbus_io_base, u32 device,
-			       u32 address, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return -2;	/* not ready */
-	}
-
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	/* output value */
-	outb(val, smbus_io_base + SMBHSTDAT0);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	return 0;
-}
-
-void alink_ab_indx(u32 reg_space, u32 reg_addr,
-			  u32 mask, u32 val)
-{
-	u32 tmp;
-
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-}
-
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port,
-			  u32 mask, u32 val)
-{
-	u32 tmp;
-
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-void alink_ax_indx(u32 space /*c or p? */, u32 axindc,
-			  u32 mask, u32 val)
-{
-	u32 tmp;
-
-	/* read axindc to tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	tmp = inl(AB_DATA);
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* write tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-}
-#endif
diff --git a/src/southbridge/amd/sb800/smbus.h b/src/southbridge/amd/sb800/smbus.h
deleted file mode 100644
index 0a7ca0e1ea..0000000000
--- a/src/southbridge/amd/sb800/smbus.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef SB800_SMBUS_H
-#define SB800_SMBUS_H
-
-#define SMBHSTSTAT 0x0
-#define SMBSLVSTAT 0x1
-#define SMBHSTCTRL 0x2
-#define SMBHSTCMD  0x3
-#define SMBHSTADDR 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBHSTBLKDAT 0x7
-
-#define SMBSLVCTRL 0x8
-#define SMBSLVCMD_SHADOW 0x9
-#define SMBSLVEVT 0xa
-#define SMBSLVDAT 0xc
-
-#define AX_INDXC  0
-#define AX_INDXP  2
-#define AXCFG     4
-#define ABCFG     6
-#define RC_INDXC  1
-#define RC_INDXP  3
-
-#define AB_INDX   0xCD8
-#define AB_DATA   (AB_INDX+4)
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100*1000*10)
-
-#define abcfg_reg(reg, mask, val)	\
-	alink_ab_indx((ABCFG), (reg), (mask), (val))
-#define axcfg_reg(reg, mask, val)	\
-	alink_ab_indx((AXCFG), (reg), (mask), (val))
-#define axindxc_reg(reg, mask, val)	\
-	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
-#define axindxp_reg(reg, mask, val)		\
-	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
-#define rcindxc_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
-#define rcindxp_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
-
-
-#endif
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
deleted file mode 100644
index 063750dc46..0000000000
--- a/src/southbridge/amd/sb800/usb.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/pci_ehci.h>
-#include <device/mmio.h>
-#include "sb800.h"
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
-};
-
-static void usb_init(struct device *dev)
-{
-	u8 byte;
-	u16 word;
-
-	/* 7.1 Enable OHCI0-4 and EHCI Controllers */
-	/* pmio 0xEF; */
-
-	/* RPR 7.2 USB S4/S5 Wake-up or PHY Power-down Support */
-	byte = pm_ioread(0xF0);
-	byte |= 1 << 0;		/* A12, USB Wake from S5 not supported on the platform */
-	pm_iowrite(0xF0, byte);
-
-	/* RPR 7.4 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
-	byte = pm_ioread(0xF0);
-	byte |= (1 << 2);
-	pm_iowrite(0xF0, byte);
-
-	/* RPR 7.9 Disable OHCI MSI Capability. */
-	word = pci_read_config16(dev, 0x40);
-	word |= (0x1 << 8);
-	pci_write_config16(dev, 0x40, word);
-}
-
-static void usb_init2(struct device *dev)
-{
-	u32 dword;
-	void *usb2_bar0;
-	struct device *sm_dev;
-
-	sm_dev = pcidev_on_root(0x14, 0);
-	//rev = get_sb800_revision(sm_dev);
-
-	/* dword = pci_read_config32(dev, 0xf8); */
-	/* dword |= 40; */
-	/* pci_write_config32(dev, 0xf8, dword); */
-
-	usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
-	printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
-
-	/* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistance */
-	dword = 0x00020F00;
-	write32(usb2_bar0 + 0xC0, dword);
-
-	/* RPR7.8 Sets In/OUT FIFO threshold for best performance */
-	dword = 0x00400040;
-	write32(usb2_bar0 + 0xA4, dword);
-
-	/* RPR7.10 Disable EHCI MSI support */
-	dword = pci_read_config32(dev, 0x50);
-	dword |= (1 << 6);
-	pci_write_config32(dev, 0x50, dword);
-
-	/* RPR7.12 EHCI Async Park Mode */
-	dword = pci_read_config32(dev, 0x50);
-	dword &= ~(0xF << 8);
-	dword &= ~(0xF << 12);
-	dword |= 1 << 8;
-	dword |= 2 << 12;
-	pci_write_config32(dev, 0x50, dword);
-
-	/* RPR 6.12 EHCI Advance PHY Power Savings */
-	/* RPR says it is just for A12. CIMM sets it when it is above A11. */
-	/* But it makes the linux crash, so we skip it */
-	#if 0
-	dword = pci_read_config32(dev, 0x50);
-	dword |= 1 << 31;
-	pci_write_config32(dev, 0x50, dword);
-	#endif
-
-	/* Each step below causes the linux crashes. Leave them here
-	 * for future debugging. */
-#if 0
-	u8 byte;
-	u16 word;
-
-
-	/* RPR6.17 Disable the EHCI Dynamic Power Saving feature */
-	word = read32(usb2_bar0 + 0xBC);
-	word &= ~(1 << 12);
-	write16(usb2_bar0 + 0xBC, word);
-
-	/* RPR6.19 USB Controller DMA Read Delay Tolerant. */
-	if (rev >= REV_SB800_A14) {
-		byte = pci_read_config8(dev, 0x50);
-		byte |= (1 << 7);
-		pci_write_config8(dev, 0x50, byte);
-	}
-
-	/* RPR6.20 Async Park Mode. */
-	/* RPR recommends not to set these bits. */
-	#if 0
-	dword = pci_read_config32(dev, 0x50);
-	dword |= 1 << 23;
-	if (rev >= REV_SB800_A14) {
-		dword &= ~(1 << 2);
-	}
-	pci_write_config32(dev, 0x50, dword);
-	#endif
-
-	/* RPR6.22 Advance Async Enhancement */
-	/* RPR6.23 USB Periodic Cache Setting */
-	dword = pci_read_config32(dev, 0x50);
-	if (rev == REV_SB800_A12) {
-		dword |= 1 << 28; /* 6.22 */
-		dword |= 1 << 27; /* 6.23 */
-	} else if (rev >= REV_SB800_A14) {
-		dword |= 1 << 3;
-		dword &= ~(1 << 28); /* 6.22 */
-		dword |= 1 << 8;
-		dword &= ~(1 << 27); /* 6.23 */
-	}
-	printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword);
-#endif
-}
-
-static struct device_operations usb_ops = {
-	.read_resources = pci_ehci_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = usb_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver usb_0_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_USB_18_0,
-};
-static const struct pci_driver usb_1_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_USB_18_2,
-};
-
-/* the pci id of usb ctrl 0 and 1 are the same. */
-/*
- * static const struct pci_driver usb_3_driver __pci_driver = {
- *	.ops = &usb_ops,
- *	.vendor = PCI_VENDOR_ID_ATI,
- *	.device = PCI_DEVICE_ID_ATI_SB800_USB_19_0,
- * };
- * static const struct pci_driver usb_4_driver __pci_driver = {
- *	.ops = &usb_ops,
- *	.vendor = PCI_VENDOR_ID_ATI,
- *	.device = PCI_DEVICE_ID_ATI_SB800_USB_19_1,
- * };
- */
-
-static const struct pci_driver usb_4_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_USB_20_5,
-};
-
-static struct device_operations usb_ops2 = {
-	.read_resources = pci_ehci_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = usb_init2,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver usb_5_driver __pci_driver = {
-	.ops = &usb_ops2,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_USB_18_2,
-};
-/*
- * static const struct pci_driver usb_5_driver __pci_driver = {
- *	.ops = &usb_ops2,
- *	.vendor = PCI_VENDOR_ID_ATI,
- *	.device = PCI_DEVICE_ID_ATI_SB800_USB_19_2,
- * };
- */