src/southbridge: Drop unneeded empty lines

Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

57 files changed, 0 insertions, 117 deletions

diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c
index ef11c861dd..ee696edb02 100644
--- a/src/southbridge/amd/agesa/hudson/fadt.c
+++ b/src/southbridge/amd/agesa/hudson/fadt.c
@@ -81,7 +81,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 
-
 	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
@@ -89,7 +88,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
-
 	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
 	fadt->x_gpe0_blk.bit_offset = 0;
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index 3609314f4e..f1506bc44f 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -13,7 +13,6 @@
 #include "smbus.h"
 #include "smi.h"
 
-
 #define PM_REG_USB_ENABLE	0xef
 
 enum usb_enable {
@@ -106,7 +105,6 @@ void hudson_enable(struct device *dev)
 	}
 }
 
-
 static void hudson_init_acpi_ports(void)
 {
 	/* We use some of these ports in SMM regardless of whether or not
diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c
index c9330df52c..5e828f7059 100644
--- a/src/southbridge/amd/agesa/hudson/pci.c
+++ b/src/southbridge/amd/agesa/hudson/pci.c
@@ -7,7 +7,6 @@
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <bootstate.h>
 
-
 /*
  * Update the PCI devices with a valid IRQ number
  * that is set in the mainboard PCI_IRQ structures.
diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h
index 5850f2ba66..6381d97e9a 100644
--- a/src/southbridge/amd/agesa/hudson/smbus.h
+++ b/src/southbridge/amd/agesa/hudson/smbus.h
@@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
 void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
 
-
 #endif
diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h
index b931cf05ab..c5ca8b40d9 100644
--- a/src/southbridge/amd/cimx/sb800/Amd.h
+++ b/src/southbridge/amd/cimx/sb800/Amd.h
@@ -83,7 +83,6 @@ typedef struct _AMD_CONFIG_PARAMS {
   IN OUT   unsigned int          Reserved[2];      ///< This space is reserved for future use.
 } AMD_CONFIG_PARAMS;
 
-
 /// AGESA Binary module header structure
 typedef struct _AMD_IMAGE_HEADER {
   IN       unsigned int  Signature;                          ///< Binary Signature
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 1bcfd6647d..99c7323033 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -48,7 +48,6 @@ typedef union _PCI_ADDR {
 #include <OEM.h>		/* platform default configuration */
 #include <AMD.h>
 
-
 //------------------------------------------------------------------------------------------------------------------------//
 /**
  * SB_CIMx_PARAMETER                0                1                   2            Default Value When CIMx Take over
diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c
index a5c27d6525..9272194442 100644
--- a/src/southbridge/amd/cimx/sb800/fadt.c
+++ b/src/southbridge/amd/cimx/sb800/fadt.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 /*
  * ACPI - create the Fixed ACPI Description Tables (FADT)
  */
@@ -112,7 +111,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
 	fadt->x_pm2_cnt_blk.addrh = 0x0;
 
-
 	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
@@ -120,7 +118,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
-
 	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
 	fadt->x_gpe0_blk.bit_offset = 0;
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index 34c32f53a7..bbba3fa083 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -39,12 +39,10 @@ void init_sb800_MANUAL_fans(struct device *dev)
 	if (sb_chip->fan4_enabled)
 		for (i = 0; i < FAN_REGISTER_COUNT; i++)
 			pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
-
 }
 
 void init_sb800_IMC_fans(struct device *dev)
 {
-
 	AMDSBCFG sb_config;
 	unsigned char *message_ptr;
 	int i;
@@ -63,7 +61,6 @@ void init_sb800_IMC_fans(struct device *dev)
 
 	pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);
 
-
 	/*
 	 * Do an initial manual setup of the fans for things like polarity
 	 * and frequency.
@@ -107,7 +104,6 @@ if (sb_chip->imc_fan_zone0_enabled) {
 	message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
 	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
 		*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
-
 }
 
 /*
@@ -138,10 +134,8 @@ if (sb_chip->imc_fan_zone1_enabled) {
 	message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
 	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
 		*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
-
 }
 
-
 /*
  ********** Zone 2 **********
  */
@@ -170,7 +164,6 @@ if (sb_chip->imc_fan_zone2_enabled) {
 	message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
 	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
 		*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
-
 }
 
 /*
@@ -202,7 +195,6 @@ if (sb_chip->imc_fan_zone3_enabled) {
 	message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
 	for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
 		*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
-
 }
 
 	/*
diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h
index 5a02543260..d11fbcfc66 100644
--- a/src/southbridge/amd/cimx/sb800/fan.h
+++ b/src/southbridge/amd/cimx/sb800/fan.h
@@ -70,7 +70,6 @@ void init_sb800_MANUAL_fans(struct device *dev);
 #define FREQ_14HZ			0xFE
 #define FREQ_11HZ			0xFF
 
-
 /* IMC Fan Control Definitions */
 #define IMC_MODE1_FAN_ENABLED					( 1 << 0 )
 #define IMC_MODE1_FAN_IMC_CONTROLLED			( 1 << 2 )
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 43a88b7cd0..15e6d67c0c 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -213,7 +213,6 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
 	.device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
 };
 
-
 static struct device_operations azalia_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
@@ -227,7 +226,6 @@ static const struct pci_driver azalia_driver __pci_driver = {
 	.device = PCI_DEVICE_ID_ATI_SB800_HDA,
 };
 
-
 static struct device_operations gec_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
@@ -358,7 +356,6 @@ static void sb800_enable(struct device *dev)
 		}
 		break;
 
-
 	case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */
 		/* Initialize the fans */
 #if CONFIG(SB800_IMC_FAN_CONTROL)
diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
index 11b24afdd9..5e5ca5d5f5 100644
--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _CIMX_H_
 #define _CIMX_H_
 
diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
index 86bde267ff..7d1ffb981e 100644
--- a/src/southbridge/amd/cimx/sb800/smbus.c
+++ b/src/southbridge/amd/cimx/sb800/smbus.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #include <arch/io.h>
 #include "smbus.h"
 #include <console/console.h>	/* printk */
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index 4a66a4b043..468ae23393 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -105,7 +105,6 @@ static void ImcSleep(void)
 	WaitForEcLDN9MailboxCmdAck();
 }
 
-
 static void ImcWakeup(void)
 {
 	u8	cmd_val = 0x96;		/* Kick off IMC Mailbox command 96 */
diff --git a/src/southbridge/amd/common/amd_defs.h b/src/southbridge/amd/common/amd_defs.h
index 3238c929c5..ca6b3ca191 100644
--- a/src/southbridge/amd/common/amd_defs.h
+++ b/src/southbridge/amd/common/amd_defs.h
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _AMD_SB_DEFS_H_
 #define _AMD_SB_DEFS_H_
 
diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c
index 319bdf380f..0bb9a97f40 100644
--- a/src/southbridge/amd/pi/hudson/fadt.c
+++ b/src/southbridge/amd/pi/hudson/fadt.c
@@ -83,7 +83,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 
-
 	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
@@ -91,7 +90,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
-
 	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
 	fadt->x_gpe0_blk.bit_offset = 0;
diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h
index a367caa910..239891065d 100644
--- a/src/southbridge/amd/pi/hudson/smbus.h
+++ b/src/southbridge/amd/pi/hudson/smbus.h
@@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
 void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
 
-
 #endif
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 1d132ee7ea..6320d2ea9f 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -202,7 +202,6 @@ int intel_early_me_init_done(u8 status)
 		timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
 	}
 
-
 	me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
 	printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
 	printk(BIOS_NOTICE, "ME:  Bist in progress: 0x%x\n", me_fws2 & 0x1);
@@ -220,7 +219,6 @@ int intel_early_me_init_done(u8 status)
 	printk(BIOS_NOTICE, "ME:  Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
 	printk(BIOS_NOTICE, "ME:  Progress code   : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
 
-
 	/* Return the requested BIOS action */
 	printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
 		me_ack_values[(hfs & 0xe) >> 1]);
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index ffd7db3f03..b0f4777d03 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
 	int c2_latency;
 
-
 	fadt->sci_int = 0x9;
 
 	if (permanent_smi_handler()) {
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 2407d92dc1..df5625afa5 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -734,7 +734,6 @@ static struct device_operations device_ops = {
 	.ops_pci		= &pci_dev_ops_pci,
 };
 
-
 /* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
  * Intel C200 Series Chipset
  */
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 5aaf661041..c26078ff6c 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -197,7 +197,6 @@ struct me_fw_version {
 	u16 recovery_hot_fix;
 } __packed;
 
-
 #define HECI_EOP_STATUS_SUCCESS       0x0
 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
 
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 7211da37a9..40672f87cd 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -142,7 +142,6 @@ void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 2));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)
diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c
index d8196f8c72..02a8375e9a 100644
--- a/src/southbridge/intel/common/pmutil.c
+++ b/src/southbridge/intel/common/pmutil.c
@@ -94,7 +94,6 @@ void dump_smi_status(u32 smi_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-
 /**
  * @brief read and clear GPE0_STS
  * @return GPE0_STS register
@@ -158,7 +157,6 @@ u32 reset_tco_status(void)
 	return reg32;
 }
 
-
 void dump_tco_status(u32 tco_sts)
 {
 	printk(BIOS_DEBUG, "TCO_STS: ");
@@ -190,7 +188,6 @@ void smi_set_eos(void)
 	write_pmbase8(SMI_EN, reg8);
 }
 
-
 void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
 {
 	int i;
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 52b83dd264..c1756474ae 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -27,7 +27,6 @@
 #define  GPI_IS_SCI		0x02
 #define  GPI_IS_NMI		0x03
 
-
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index 06d7c74e58..0dbc48cea5 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #include <device/device.h>
 #include <device/pci.h>
 #include <console/console.h>
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 49e306f667..7610aa1102 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -95,7 +95,6 @@ __weak void southbridge_smm_xhci_sleep(u8 slp_type)
 {
 }
 
-
 static void southbridge_smi_sleep(void)
 {
 	u8 reg8;
@@ -388,8 +387,6 @@ static void southbridge_smi_mc(void)
 	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
 
-
-
 static void southbridge_smi_tco(void)
 {
 	u32 tco_sts;
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 380940c739..757f0acc48 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -718,7 +718,6 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
 	return 0;
 }
 
-
 static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
 			size_t len)
 {
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 9064a1238c..988d7418d3 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -92,7 +92,6 @@ static void pwrmgt_read_resources(struct device *dev)
 	             IORESOURCE_RESERVE;
 }
 
-
 static const struct smbus_bus_operations lops_smbus_bus = {
 };
 
diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c
index 7adfa9618d..d6a6bc9864 100644
--- a/src/southbridge/intel/i82801dx/ac97.c
+++ b/src/southbridge/intel/i82801dx/ac97.c
@@ -33,7 +33,6 @@
 #define MBAR		0x14
 #define   SEC_CODEC	0x40
 
-
 /* FIXME. This table is probably mainboard specific */
 static u16 ac97_function[16*2][4] = {
 	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c
index 9239383c03..84ea73ad9c 100644
--- a/src/southbridge/intel/i82801dx/fadt.c
+++ b/src/southbridge/intel/i82801dx/fadt.c
@@ -20,7 +20,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
 	u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
 
-
 	fadt->sci_int = 0x9;
 
 	if (permanent_smi_handler()) {
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index d5790ae13b..9864720ad0 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -46,8 +46,6 @@ void aseg_smm_lock(void);
 /* IDE_TIM bits */
 #define IDE_DECODE_ENABLE	(1 << 15)
 
-
-
 #define PCI_DMA_CFG     0x90
 #define SERIRQ_CNTL     0x64
 #define GEN_CNTL        0xd0
@@ -93,7 +91,6 @@ void aseg_smm_lock(void);
 
 #define RTC_FAILED      (1 <<2)
 
-
 #define PM1_STS		0x00
 #define   WAK_STS	(1 << 15)
 #define   PCIEXPWAK_STS	(1 << 14)
diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c
index 26bbbe143d..dd993cedb0 100644
--- a/src/southbridge/intel/i82801dx/smi.c
+++ b/src/southbridge/intel/i82801dx/smi.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #include <device/device.h>
 #include <device/pci.h>
 #include <console/console.h>
@@ -13,7 +12,6 @@
 #include <string.h>
 #include "i82801dx.h"
 
-
 void northbridge_write_smram(u8 smram);
 
 /* For intel/e7505. */
@@ -98,7 +96,6 @@ static void dump_smi_status(u32 smi_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-
 /**
  * @brief read and clear GPE0_STS
  * @return GPE0_STS register
@@ -138,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-
 /**
  * @brief read and clear ALT_GP_SMI_STS
  * @return ALT_GP_SMI_STS register
@@ -164,8 +160,6 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-
-
 /**
  * @brief read and clear TCOx_STS
  * @return TCOx_STS registers
@@ -184,7 +178,6 @@ static u32 reset_tco_status(void)
 	return reg32;
 }
 
-
 static void dump_tco_status(u32 tco_sts)
 {
 	printk(BIOS_DEBUG, "TCO_STS: ");
@@ -204,8 +197,6 @@ static void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-
-
 /**
  * @brief Set the EOS bit
  */
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index af56941407..19fe5bba2a 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -96,7 +96,6 @@ static void dump_smi_status(u32 smi_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-
 /**
  * @brief read and clear GPE0_STS
  * @return GPE0_STS register
@@ -136,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-
 /**
  * @brief read and clear TCOx_STS
  * @return TCOx_STS registers
@@ -155,7 +153,6 @@ static u32 reset_tco_status(void)
 	return reg32;
 }
 
-
 static void dump_tco_status(u32 tco_sts)
 {
 	printk(BIOS_DEBUG, "TCO_STS: ");
@@ -222,7 +219,6 @@ static void busmaster_disable_on_bus(int bus)
 	}
 }
 
-
 static void southbridge_smi_sleep(void)
 {
 	u8 reg8;
@@ -389,8 +385,6 @@ static void southbridge_smi_mc(void)
 	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
 
-
-
 static void southbridge_smi_tco(void)
 {
 	u32 tco_sts;
diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c
index cc6e376130..5230ace8ef 100644
--- a/src/southbridge/intel/i82801gx/ac97.c
+++ b/src/southbridge/intel/i82801gx/ac97.c
@@ -34,7 +34,6 @@
 #define MBAR		0x14
 #define   SEC_CODEC	0x40
 
-
 /* FIXME. This table is probably mainboard specific */
 static u16 ac97_function[16*2][4] = {
 	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 90a70e483b..eb59eb031c 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -411,7 +411,6 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 		 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
 
-
 	return current;
 }
 
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index 9624b9862f..5915f3d15b 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -58,7 +58,6 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
 	return do_smbus_block_read(res->base, device, cmd, bytes, buf);
 }
 
-
 static struct smbus_bus_operations lops_smbus_bus = {
 	.read_byte	= lsmbus_read_byte,
 	.write_byte	= lsmbus_write_byte,
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 562dae3a97..f1be5c200b 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -58,7 +58,6 @@ void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 2));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c
index ffc57f2e1a..cbb52c4a6c 100644
--- a/src/southbridge/intel/i82801ix/dmi_setup.c
+++ b/src/southbridge/intel/i82801ix/dmi_setup.c
@@ -38,7 +38,6 @@ void i82801ix_dmi_setup(void)
 	RCBA8(RCBA_BCR)   = 0x45;
 	RCBA32(RCBA_CIR6) &= ~(1 << 7);
 
-
 	/* VC1 setup for isochronous transfers: */
 
 	/* Set VC1 virtual channel id to 1. */
@@ -60,7 +59,6 @@ void i82801ix_dmi_setup(void)
 	/* Enable VC1. */
 	RCBA32(RCBA_V1CTL) |= (1 << 31);
 
-
 	/* Setup RCRB: */
 
 	/* Set component id to 2 for southbridge, northbridge has id 1. */
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 3bd1d49869..56f14b0d2f 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -20,11 +20,8 @@
 #define DEFAULT_TCOBASE		(DEFAULT_PMBASE + 0x60)
 #define DEFAULT_GPIOBASE	0x00000580
 
-
 #define APM_CNT		0xb2
 
-
-
 #define GP_IO_USE_SEL	0x00
 #define GP_IO_SEL	0x04
 #define GP_LVL		0x0c
@@ -73,23 +70,19 @@
 #define D31F0_CxSTATE_CNF	0xa9
 #define D31F0_C4TIMING_CNT	0xaa
 
-
 /* D31:F2 SATA */
 #define D31F2_IDE_TIM_PRI	0x40
 #define D31F2_IDE_TIM_SEC	0x42
 #define D31F2_SIDX		0xa0
 #define D31F2_SDAT		0xa4
 
-
 /* D30:F0 PCI-to-PCI bridge */
 #define D30F0_SMLT		0x1b
 
-
 /* D28:F0-5 PCIe root ports */
 #define D28Fx_XCAP		0x42
 #define D28Fx_SLCAP		0x54
 
-
 /* PCI Configuration Space (D31:F3): SMBus */
 #define SMB_BASE		0x20
 #define HOSTC			0x40
@@ -154,7 +147,6 @@
 #define FD_SD		(1 <<  3) /* SMBus */
 #define FD_SAD1		(1 <<  2) /* SATA #1 */
 
-
 #ifndef __ACPI__
 #ifndef __ASSEMBLER__
 
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c
index 4f47e34142..1abd8c5a55 100644
--- a/src/southbridge/intel/i82801ix/smi.c
+++ b/src/southbridge/intel/i82801ix/smi.c
@@ -114,7 +114,6 @@ static void aseg_smm_install(void)
 		return;
 	smm_handler_copied = 1;
 
-
 	/* if we're resuming from S3, the SMM code is already in place,
 	 * so don't copy it again to keep the current SMM state */
 
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 699f51f712..537e544f94 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -51,7 +51,6 @@ void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 3));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index b3cab9154a..22546897a7 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -11,11 +11,8 @@
 #define DEFAULT_TCOBASE		(DEFAULT_PMBASE + 0x60)
 #define DEFAULT_GPIOBASE	0x00000580
 
-
 #define APM_CNT		0xb2
 
-
-
 #define GP_IO_USE_SEL	0x00
 #define GP_IO_SEL	0x04
 #define GP_LVL		0x0c
@@ -66,23 +63,19 @@
 #define D31F0_C4TIMING_CNT	0xaa
 #define D31F0_GPIO_ROUT		0xb8
 
-
 /* D31:F2 SATA */
 #define D31F2_IDE_TIM_PRI	0x40
 #define D31F2_IDE_TIM_SEC	0x42
 #define D31F2_SIDX		0xa0
 #define D31F2_SDAT		0xa4
 
-
 /* D30:F0 PCI-to-PCI bridge */
 #define D30F0_SMLT		0x1b
 
-
 /* D28:F0-5 PCIe root ports */
 #define D28Fx_XCAP		0x42
 #define D28Fx_SLCAP		0x54
 
-
 /* PCI Configuration Space (D31:F3): SMBus */
 #define SMB_BASE		0x20
 #define HOSTC			0x40
@@ -164,7 +157,6 @@
 #define FD_SD		(1 <<  3) /* SMBus */
 #define FD_SAD1		(1 <<  2) /* SATA #1 */
 
-
 #ifndef __ACPI__
 
 #include <device/pci_ops.h>
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 3bed5ddcc2..2f7b516a2a 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -408,7 +408,6 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 		 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
 
-
 	return current;
 }
 
diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c
index 16ec025c15..7d79620114 100644
--- a/src/southbridge/intel/i82801jx/smihandler.c
+++ b/src/southbridge/intel/i82801jx/smihandler.c
@@ -52,7 +52,6 @@ void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 3));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)
diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c
index 6ef14a3b08..944378eca4 100644
--- a/src/southbridge/intel/ibexpeak/bootblock.c
+++ b/src/southbridge/intel/ibexpeak/bootblock.c
@@ -74,7 +74,6 @@ static void early_lpc_init(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 }
 
-
 void bootblock_early_southbridge_init(void)
 {
 	enable_spi_prefetching_and_caching();
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index a0dcee8931..ccd9f57b74 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
 	int c2_latency;
 
-
 	fadt->sci_int = 0x9;
 
 	if (permanent_smi_handler()) {
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 230d5eb29f..1ede5d6bdb 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -618,7 +618,6 @@ static struct device_operations device_ops = {
 	.ops_pci		= &pci_dev_ops_pci,
 };
 
-
 static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_IBEXPEAK_LPC_QM57,
 	PCI_DID_INTEL_IBEXPEAK_LPC_HM55,
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 2c9c87cbcc..3477d8cfc2 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -604,7 +604,6 @@ static const unsigned short pci_device_ids[] = {
 	0
 };
 
-
 static const struct pci_driver intel_me __pci_driver = {
 	.ops	= &device_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h
index beacd3358a..2466d02943 100644
--- a/src/southbridge/intel/ibexpeak/me.h
+++ b/src/southbridge/intel/ibexpeak/me.h
@@ -198,7 +198,6 @@ struct me_fw_version {
 	u16 recovery_hot_fix;
 } __packed;
 
-
 #define HECI_EOP_STATUS_SUCCESS       0x0
 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
 
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 6c3f349ce3..3ca85c51f1 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -107,7 +107,6 @@ void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 2));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 7ad9929001..a2adc5aab7 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -66,7 +66,6 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
 	pci_write_config8(dev, 0x80, access_cntl);
 }
 
-
 static struct pci_operations lops_pci = {
 	.set_subsystem = &usb_ehci_set_subsystem,
 };
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index cba7671ecc..e30d4b4c21 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -91,5 +91,4 @@ struct southbridge_intel_lynxpoint_config {
 	bool docking_supported;
 };
 
-
 #endif				/* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index c85ba2c616..448ee8bd68 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -19,7 +19,6 @@ static u16 get_gpio_base(void)
 #endif
 }
 
-
 /*
  * This function will return a number that indicates which PIRQ
  * this GPIO maps to.  If this is not a PIRQ capable GPIO then
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a9fa61fb43..e5614303cc 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -791,7 +791,6 @@ static struct device_operations device_ops = {
 	.ops_pci		= &pci_dev_ops_pci,
 };
 
-
 /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
 static const unsigned short pci_device_ids[] = {
 	0x8c41, /* Mobile Full Featured Engineering Sample. */
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 8c4a8c1c90..af7a2b2b98 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -57,7 +57,6 @@ static void print_gpio_status(u32 status, int start)
 	}
 }
 
-
 /*
  * PM1_CNT
  */
@@ -78,7 +77,6 @@ void disable_pm1_control(u32 mask)
 	outl(pm1_cnt, get_pmbase() + PM1_CNT);
 }
 
-
 /*
  * PM1
  */
@@ -127,7 +125,6 @@ void enable_pm1(u16 events)
 	outw(events, get_pmbase() + PM1_EN);
 }
 
-
 /*
  * SMI
  */
@@ -198,7 +195,6 @@ void disable_smi(u32 mask)
 	outl(smi_en, get_pmbase() + SMI_EN);
 }
 
-
 /*
  * ALT_GP_SMI
  */
@@ -298,7 +294,6 @@ void enable_alt_smi(u32 mask)
 	}
 }
 
-
 /*
  * TCO
  */
@@ -368,7 +363,6 @@ void enable_tco_sci(void)
 	enable_gpe(TCOSCI_EN);
 }
 
-
 /*
  * GPE0
  */
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 5ccb229805..f5c5f2a80e 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -78,7 +78,6 @@ static void busmaster_disable_on_bus(int bus)
 	}
 }
 
-
 static void southbridge_smi_sleep(void)
 {
 	u8 reg8;
@@ -379,8 +378,6 @@ static void southbridge_smi_mc(void)
 	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
 
-
-
 static void southbridge_smi_tco(void)
 {
 	u32 tco_sts = clear_tco_status();
@@ -443,7 +440,6 @@ static void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 2));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index 73cb2e1fda..e0744b314e 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -107,11 +107,9 @@ static void rl5c476_init(struct device *dev)
 	pc16->moffl0 = 0;
 	pc16->moffh0 = 0x40;
 
-
 	/* set I/O width for Auto Data width */
 	pc16->ioctrl = 0x22;
 
-
 	/* enable I/O window 0 and 1 */
 	pc16->awinen = 0xc1;
 
@@ -125,7 +123,6 @@ static void rl5c476_init(struct device *dev)
 
 	pc16->igctrl = 0x69;
 
-
 	/* 16 bit CF always have first config byte at 0x200 into
 	 * Config structure, but CF+ may not according to spec -
 	 * should locate through reading tuple data, but this should
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h
index 4f5ecdc8bf..e27e7a383f 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.h
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.h
@@ -2,10 +2,8 @@
 
  /* rl5c476 routines and defines*/
 
-
 #include <stdint.h>
 
-
 /* the 16 bit control structure for ricoh cardbus bridge */
 typedef struct pc16reg  {
 	u8 idrevs;