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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-01-18 12:26:13 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-02-10 19:33:25 +0100
commit089b88c165468367e176d5bcc022b3702f499234 (patch)
tree639fe5f5ac3da3f3be372766029d224855aa9675 /src/southbridge
parent0108bf5157de24619f644721a82775d578087573 (diff)
usbdebug: Remove duplicate port claim
This claim is useless when done before EHCI controller reset. Code in usbdebug_init_() already sets this properly after reset, see use of DBGP_OWNER. Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4709 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/common/usb_debug.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index fecd716fdd..d18cb0fe12 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -64,8 +64,6 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- u32 dbgctl;
-
/* Bail out. No console to complain in. */
if (!dev)
return;
@@ -75,9 +73,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
- /* Force ownership of the Debug Port to the EHCI controller. */
- dbgctl = read32(base + CONFIG_EHCI_DEBUG_OFFSET);
- dbgctl |= (1 << 30);
- write32(base + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
}