diff options
| author | Marek Maslanka <mmaslanka@google.com> | 2024-01-17 14:57:36 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-30 13:28:39 +0000 |
| commit | 06798cd53f832d5551748d892921df3132b8e659 (patch) | |
| tree | 1ec70bd0fa4b179db036202ab538233f25b157ea /src/southbridge | |
| parent | 33387eb23dc63a7382b1cb0f86c2c4ae510df153 (diff) | |
soc/intel: Unify the definition of TCO registers
Move the definition of the TCO registers used in most boards to a
separate file and use it consistently. Do not unify TCO for older
incompatible platforms.
BUG=b:314260167
TEST=none
Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/common/tco.h | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/common/watchdog.c | 4 |
2 files changed, 4 insertions, 9 deletions
diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 5bf386f1c2..b586fe5aa7 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -10,13 +10,8 @@ #undef TCO1_CNT #endif -#define PMBASE_TCO_OFFSET 0x60 +#include <soc/intel/common/tco.h> -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO1_CNT 0x08 -#define TCO_TMR_HLT (1 << 11) +#define PMBASE_TCO_OFFSET 0x60 #endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 1c43a0cd9b..36b9525f13 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -27,11 +27,11 @@ void watchdog_off(void) /* Disable the watchdog timer. */ value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); - value |= TCO_TMR_HLT; + value |= TCO1_TMR_HLT; write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); /* Clear TCO timeout status. */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_STS_TIMEOUT); write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO); printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); |