diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 00:36:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-07 20:20:00 +0000 |
| commit | f462b3d379198c968467053f570d6a40c9c8a715 (patch) | |
| tree | 06da018e6740df91f9d7fcbd9d18fa600efcc2dd /src/southbridge | |
| parent | dd1fb4e38c209f4713d80ae192bd8f4cb4ed0e32 (diff) | |
nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
These accessors can be reused for several other northbridges.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801ix/dmi_setup.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index cbb52c4a6c..f8b418d9df 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <console/console.h> -#include <northbridge/intel/gm45/gm45.h> #include "i82801ix.h" /* VC1 Port Arbitration Table */ @@ -67,7 +66,7 @@ void i82801ix_dmi_setup(void) RCBA8(RCBA_ULD + 3) = 1; RCBA8(RCBA_ULD + 2) = 1; /* Set target rcrb base address, i.e. DMIBAR. */ - RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR; + RCBA32(RCBA_ULBA) = (uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE; /* Enable ASPM. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { |