Fall back to pre-broken settings and setup for GX2.

We lost a few things, but this is still worth it.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 1 insertions, 4 deletions

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index ebe99cf395..37c54d5c50 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -29,13 +29,11 @@ static void southbridge_enable(struct device *dev)
 		msr.lo = sb->lpc_serirq_enable;
 		msr.hi  = 0;
 		wrmsr(MDD_LPC_SIRQ, msr);
-		printk_debug("Enabled LPC SERIRQ 0x%x\n", msr.lo);
 	}
 	if (sb->lpc_irq) {
 		msr.lo = sb->lpc_irq;
 		msr.hi = 0;
 		wrmsr(MDD_IRQM_LPC, msr);
-		printk_debug("Enabled  lpc irq values 0x%x\n", msr.lo);
 	}
 
 	if (sb->enable_gpio0_inta){
@@ -49,7 +47,6 @@ static void southbridge_enable(struct device *dev)
 		/* magic stuff */
 		outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
 		outl(GPIOL_0_SET, GPIO_MAPPER_X);
-		printk_debug("Enabled GPIO0 INTa\n");
 	}
 		
 	
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index d66802076d..eb8f9f5140 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -165,7 +165,7 @@ static int cs5536_setup_onchipuart(void)
 	 *    MSR 0x51400014 bit 18:16
 	 * 3. Enable UART controller
 	 *    MSR 0x5140003A bit 0, 1
-	 * 4. IRQ routing on IRQ Mapper (before loading OS)
+	 * 4. IRQ routing on IRQ Mapper
 	 *    MSR 0x51400021 bit [27:24]
 	 */
 	msr_t msr;