diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-02-17 13:08:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 13:04:20 +0000 |
| commit | 95de2317c6c6379e43d3b3c27d34eb66198dbe0a (patch) | |
| tree | e0df0c7dfce199b95609be41f0d806b5829d8005 /src/southbridge | |
| parent | 2aff3005e0ebdf99c0a0f063f023536f601a879b (diff) | |
nb/intel/nehalem: Rename to ironlake
The code is for Arrandale CPUs, whose System Agent is Ironlake.
This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.
Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/common/firmware/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_cir.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/smihandler.c | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index eb63d34520..134f780825 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -59,7 +59,7 @@ config ME_BIN_PATH config CHECK_ME bool "Verify the integrity of the supplied ME/TXE firmware" default n - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ @@ -71,7 +71,7 @@ config CHECK_ME config USE_ME_CLEANER bool "Strip down the Intel ME/TXE firmware" - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c index 8d7a918d40..9aac07b075 100644 --- a/src/southbridge/intel/ibexpeak/early_cir.c +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -14,7 +14,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include "pch.h" /* This sets up magic Chipset Initialization Registers */ @@ -53,7 +53,7 @@ void pch_setup_cir(int chipset_type) /* Intel 5 Series Chipset and Intel 3400 Series Chipset External Design Specification (EDS) 13.8.1.1 */ - if (chipset_type == NEHALEM_DESKTOP) + if (chipset_type == IRONLAKE_DESKTOP) pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 56331cc696..b455cef179 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> @@ -47,7 +47,7 @@ void early_pch_init(void) early_gpio_init(); enable_smbus(); /* TODO, make this configurable */ - pch_setup_cir(NEHALEM_MOBILE); + pch_setup_cir(IRONLAKE_MOBILE); southbridge_configure_default_intmap(); pch_default_disable(); early_usb_init(mainboard_usb_ports); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 39881889f1..e670c9ade4 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -34,7 +34,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmutil.h> @@ -185,6 +185,6 @@ void southbridge_finalize_all(void) { intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); + intel_ironlake_finalize_smm(); intel_model_2065x_finalize_smm(); } |