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authorRonald G. Minnich <rminnich@gmail.com>2006-06-22 04:37:27 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-06-22 04:37:27 +0000
commit88fb1a6c371c9f368157bdb907f70d46bb670311 (patch)
treee15de2e82954df04eeacd055471c278c93b55f4f /src/southbridge
parent9d0b30dd2b33d04859986be85b125c3005b2a277 (diff)
set up interrupt values for the southbridge, and add a function to
manage them. Make pci_level_irq global. Add value settings for OLPC rev_a board. Comment out no-longer-needed code in olpc mainboard.c -- it is replaced by the settings in Config.lb, and the support in cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5536/chip.h8
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c24
2 files changed, 31 insertions, 1 deletions
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h
index 33cc78a2f1..c186ff31d7 100644
--- a/src/southbridge/amd/cs5536/chip.h
+++ b/src/southbridge/amd/cs5536/chip.h
@@ -10,6 +10,14 @@ struct southbridge_amd_cs5536_config {
int enable_gpio0_inta; /* almost always will be true */
int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */
int enable_uarta; /* internal uarta interrupt enable */
+ /* following are IRQ numbers for various southbridge resources. */
+ /* I have guessed at some things, as I still don't have an lspci from anyone */
+ int ide_irq; /* f.2 */
+ int audio_irq; /* f.3 */
+ int usbf4_irq; /* f.4 */
+ int usbf5_irq; /* f.5 */
+ int usbf6_irq; /* f.6 */
+ int usbf7_irq; /* f.7 */
};
#endif /* _SOUTHBRIDGE_AMD_CS5536 */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 062ba5a0f0..b67211fa0d 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -63,6 +63,21 @@ enable_ide_nand_flash(){
printk_err("cs5536: EXIT %s\n", __FUNCTION__);
}
+/* note: this is a candidate for inclusion in src/devices/pci_device.c */
+void
+setup_irq(unsigned irq, char *name, unsigned level, unsigned bus, unsigned device, unsigned fn){
+ if (irq) {
+ unsigned devfn = PCI_DEVFN(device,fn);
+ device_t dev = dev_find_slot(bus, devfn);
+ if (dev) {
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, irq);
+ if (level)
+ pci_level_irq(irq);
+ }
+ else
+ printk_err("%s: Can't find %s at 0x%x\n", __FUNCTION__, name, devfn);
+ }
+}
static void southbridge_enable(struct device *dev)
{
@@ -109,7 +124,14 @@ static void southbridge_enable(struct device *dev)
printk_err("%s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
if (sb->enable_ide_nand_flash) {
enable_ide_nand_flash();
- }
+ }
+
+ /* irq handling */
+ setup_irq(sb->audio_irq, "audio", 1, 0, 0xf, 2);
+ setup_irq(sb->usbf4_irq, "usb f4", 1, 0, 0xf, 4);
+ setup_irq(sb->usbf5_irq, "usb f5", 1, 0, 0xf, 5);
+ setup_irq(sb->usbf6_irq, "usb f6", 1, 0, 0xf, 6);
+ setup_irq(sb->usbf7_irq, "usb f7", 1, 0, 0xf, 7);
}