soc/intel/apl: Configure LPC serial IRQ mode

Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.

TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
     works correctly now, but was confused by the wrong settings before
     because the FSP defaults allowed to disable the LPC clock.

Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

0 files changed, 0 insertions, 0 deletions