diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2013-04-10 11:33:37 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@se-eng.com> | 2013-04-11 22:04:20 +0200 |
| commit | 6a1210901dff47a65dac157445f0a76219be0d55 (patch) | |
| tree | fc30343879c7b813f6b9b7b38931036ca968eb8a /src/southbridge | |
| parent | 573a1d6fa8d72e6d3f738bb889a34b405952046c (diff) | |
AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment
Reading the paste of code in a message to the mailing list [1],
a typo was spotted and found in one more place.
$ git grep egnoring
src/southbridge/amd/rs780/cmn.c: * egnoring the reversal case
src/southbridge/amd/sr5650/sr5650.c: * egnoring the reversal case
These typos are there since when the code was committed and are
now corrected.
[1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html
Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3062
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/rs780/cmn.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/sr5650.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 3c6d22dda5..cf09b9a89d 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -301,7 +301,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) /* 4 means 7:4 and 15:12 * 3 means 7:2 and 15:10 * 2 means 7:1 and 15:9 - * egnoring the reversal case + * ignoring the reversal case */ lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 0bb246e9ed..7fdecf1dae 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -202,7 +202,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) /* 4 means 7:4 and 15:12 * 3 means 7:2 and 15:10 * 2 means 7:1 and 15:9 - * egnoring the reversal case + * ignoring the reversal case */ lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel); |