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authorEric Biederman <ebiederm@xmission.com>2003-06-12 17:55:54 +0000
committerEric Biederman <ebiederm@xmission.com>2003-06-12 17:55:54 +0000
commit540ae01cd341de75f5eb57906699ca24667d71cc (patch)
tree19b50f63003cea377301d19228f79391e89403fd /src/southbridge
parent05f26fcb571340b17beaca16939a025a9c0b4cdd (diff)
- Changes to the pci config routines moving them closer to the non romcc API
The goal is to have the same interface with or without romcc. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/amd8111/amd8111_early_smbus.c12
-rw-r--r--src/southbridge/amd/amd8111/amd8111_enable_rom.c9
2 files changed, 9 insertions, 12 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c
index b0b8e4955f..6b6d9ad144 100644
--- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c
+++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c
@@ -11,16 +11,16 @@
static void enable_smbus(void)
{
- uint32_t addr;
- addr = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
- if (addr == ~0U) {
+ device_t dev;
+ dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
+ if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n");
}
uint8_t enable;
print_debug("SMBus controller enabled\r\n");
- pci_write_config32(addr + 0x58, SMBUS_IO_BASE | 1);
- enable = pci_read_config8(addr + 0x41);
- pci_write_config8(addr + 0x41, enable | (1 << 7));
+ pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
+ enable = pci_read_config8(dev, 0x41);
+ pci_write_config8(dev, 0x41, enable | (1 << 7));
}
diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
index d6045c3620..4aea04ccf5 100644
--- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c
+++ b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
@@ -2,17 +2,14 @@
static void amd8111_enable_rom(void)
{
unsigned char byte;
- uint32_t addr;
+ device_t addr;
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
/* Locate the amd8111 */
addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
- /* Refine the address to point at the rom enable byte */
- addr += 0x43;
-
/* Set the 4MB enable bit bit */
- byte = pci_read_config8(addr);
+ byte = pci_read_config8(addr, 0x43);
byte |= 0x80;
- pci_write_config8(addr, byte);
+ pci_write_config8(addr, 0x43, byte);
}