diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-09-19 17:24:55 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 10:47:02 +0200 |
| commit | 401bd31b2d9efed119d82eb4c153bd273fe64b49 (patch) | |
| tree | a3d6d8fcb9c9818522fb0848d3f0e2f257d331e1 /src/southbridge | |
| parent | 94cc485338a30c50c74a7bb02d14a52f35ff41c3 (diff) | |
mainboard/google/reef: Enable cr50 TPM interrupt
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage. The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16673
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions