diff options
| author | Joseph Smith <joe@settoplinux.org> | 2010-06-21 23:25:06 +0000 |
|---|---|---|
| committer | Joseph Smith <joe@smittys.pointclark.net> | 2010-06-21 23:25:06 +0000 |
| commit | b94a79fa6a7a9fa2e4dae9f38fc5c67aeaee09c9 (patch) | |
| tree | 2135a03ee0d7d0e5f6e4053dcbcc4d64fdb136f4 /src/southbridge | |
| parent | 40bffc22cd6b83b186c023d473e6213a65c2d51d (diff) | |
This patch adds support for the Intel D810E2CB (i810e/ICH2) desktop board. Hurray, this is the first i810 board running CAR.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801bx/i82801bx.h | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801bx/i82801bx_lpc.c | 19 |
2 files changed, 9 insertions, 18 deletions
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h index 8c2c30794c..70f573f96c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx.h +++ b/src/southbridge/intel/i82801bx/i82801bx.h @@ -37,10 +37,8 @@ extern void i82801bx_enable(device_t dev); #define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */ #define ACPI_CNTL 0x44 #define BIOS_CNTL 0x4E -#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */ -#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */ -#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */ -#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */ +#define GPIO_BASE 0x58 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x5C /* LPC GPIO Control Register */ #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 @@ -69,6 +67,8 @@ extern void i82801bx_enable(device_t dev); #define MTT 0x70 #define PCI_MAST_STS 0x82 +#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ + #define TCOBASE 0x60 /* TCO Base Address Register */ #define TCO1_CNT 0x08 /* TCO1 Control Register */ diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c index 59511dfe46..241eb52f4c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c +++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c @@ -32,8 +32,6 @@ #include <arch/io.h> #include "i82801bx.h" -#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ - #define NMI_OFF 0 typedef struct southbridge_intel_i82801bx_config config_t; @@ -206,18 +204,11 @@ static void i82801bx_power_options(device_t dev) } } -static void gpio_init(device_t dev, uint16_t ich_model) +static void gpio_init(device_t dev) { - /* Set the value for GPIO base address register and enable GPIO. - * Note: ICH-ICH5 registers differ from ICH6-ICH9. - */ - if (ich_model <= 0x24D0) { - pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); - } else if (ich_model >= 0x2640) { - pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10); - } + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); } void i82801bx_rtc_init(struct device *dev) @@ -291,7 +282,7 @@ static void lpc_init(struct device *dev) i82801bx_power_options(dev); /* Set the state of the GPIO lines. */ - gpio_init(dev, ich_model); + gpio_init(dev); /* Initialize the real time clock. */ i82801bx_rtc_init(dev); |