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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-02-24 11:30:38 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-04-30 01:33:10 +0200 |
| commit | b8179087afea63bc10c950eb3406b4fc94a3997f (patch) | |
| tree | 7ddd425d320361d2fbbe53a088a98431bede349f /src/southbridge | |
| parent | bdd98254abf964692f193fe42ebffbd01d0b22b8 (diff) | |
cbmem: Add FSP timestamps
Add additional FSP timestamp values to cbmem.h and specify values for
the existing ones. Update cbmem.c with the FSP timestamp values and
descriptions.
BRANCH=none
BUG=None
TEST=Build for Braswell and Skylake boards using FSP 1.1.
Change-Id: I835bb090ff5877a108e48cb60f8e80260773771b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10025
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions