Convert some comments to proper Doxygen syntax.

Also, make them all fit in 80chars/column, fix some whitespace issues
and also some typos I noticed.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 43 insertions, 54 deletions

diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h
index e0d377a9cd..da518a3660 100644
--- a/src/southbridge/intel/i82801cx/i82801cx.h
+++ b/src/southbridge/intel/i82801cx/i82801cx.h
@@ -32,9 +32,7 @@ void i82801cx_hard_reset(void);
 #define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
 
-/********************************************************************/
-/*							IDE Controller                          */
-/********************************************************************/
+/* IDE controller: */
 
 // PCI Configuration Space (D31:F1)
 #define IDE_TIM_PRI		0x40		// IDE timings, primary
@@ -44,9 +42,7 @@ void i82801cx_hard_reset(void);
 // IDE_TIM bits
 #define IDE_DECODE_ENABLE	(1<<15)
 
-/********************************************************************/
-/*								SMBus                               */
-/********************************************************************/
+/* SMBus: */
 
 // PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20
diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
index 2f2c4600a2..a1ffb8f540 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
@@ -61,15 +61,14 @@ static void i82801cx_enable_serial_irqs( struct device *dev)
     pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	i82801cx_lpc_route_dma
-// Parameters:  	dev
-//					mask - identifies whether each channel should be used for PCI DMA
-//						   (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-//						   Channel 4 is not used (reserved).
-// Return Value:	None
-// Description: 	Route all DMA channels to either PCI or LPC.
-//
+/**
+ * Route all DMA channels to either PCI or LPC.
+ *
+ * @param dev TODO
+ * @param mask Identifies whether each channel should be used for PCI DMA
+ *             (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
+ *             Channel 4 is not used (reserved).
+ */
 static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
 {
     uint16_t dmaConfig;
diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c
index 0f998dda9e..8af57beed7 100644
--- a/src/southbridge/intel/i82870/p64h2_ioapic.c
+++ b/src/southbridge/intel/i82870/p64h2_ioapic.c
@@ -18,15 +18,15 @@ static void p64h2_ioapic_enable(device_t dev)
     pci_write_config16(dev, PCI_COMMAND, command);
 }
 
-//----------------------------------------------------------------------------------
-// Function:        p64h2_ioapic_init
-// Parameters:      dev - PCI bus/device/function of P64H2 IOAPIC
-//                  NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0
-// Return Value:    None
-// Description:     Configure one of the IOAPICs in a P64H2.
-//                  Note that a PCI bus scan will detect both IOAPICs, so this function
-//                  will be called twice for each P64H2 in the system.
-//
+/**
+ * Configure one of the IOAPICs in a P64H2.
+ *
+ * Note that a PCI bus scan will detect both IOAPICs, so this function
+ * will be called twice for each P64H2 in the system.
+ *
+ * @param dev PCI bus/device/function of P64H2 IOAPIC.
+ *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
+ */
 static void p64h2_ioapic_init(device_t dev)
 {
     uint32_t memoryBase;
diff --git a/src/southbridge/sis/sis966/sis761.c b/src/southbridge/sis/sis966/sis761.c
index f1d1fe26d8..3d7bc470d3 100644
--- a/src/southbridge/sis/sis966/sis761.c
+++ b/src/southbridge/sis/sis966/sis761.c
@@ -41,22 +41,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <arch/io.h>
 
-/**
- * @brief Read resources for AGP aperture
- *
- * @param
- *
- * There is only one AGP aperture resource needed. The resoruce is added to
- * the northbridge of BSP.
- *
- * The same trick can be used to augment legacy VGA resources which can
- * be detect by generic pci reousrce allocator for VGA devices.
- * BAD: it is more tricky than I think, the resource allocation code is
- * implemented in a way to NOT DOING legacy VGA resource allcation on
- * purpose :-(.
- */
-
-
 typedef struct msr_struct
 {
 	unsigned lo;
@@ -71,6 +55,20 @@ static inline msr_t rdmsr(unsigned index)
 	return result;
 }
 
+/**
+ * Read resources for AGP aperture.
+ *
+ * There is only one AGP aperture resource needed. The resoruce is added to
+ * the northbridge of BSP.
+ *
+ * The same trick can be used to augment legacy VGA resources which can
+ * be detect by generic PCI resource allocator for VGA devices.
+ * BAD: it is more tricky than I think, the resource allocation code is
+ * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * purpose :-(.
+ *
+ * @param dev TODO
+ */
 static void sis761_read_resources(device_t dev)
 {
 	/* Read the generic PCI resources */
diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c
index c6a1fce20d..26f60dd3af 100644
--- a/src/southbridge/sis/sis966/sis966_lpc.c
+++ b/src/southbridge/sis/sis966/sis966_lpc.c
@@ -184,10 +184,9 @@ static void sis966_lpc_read_resources(device_t dev)
 }
 
 /**
- * @brief Enable resources for children devices
- *
- * @param dev the device whos children's resources are to be enabled
+ * Enable resources for children devices.
  *
+ * @param dev The device whos children's resources are to be enabled.
  */
 static void sis966_lpc_enable_childrens_resources(device_t dev)
 {
diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/sis966_nic.c
index 7b1a856c8d..a7aeec37ed 100644
--- a/src/southbridge/sis/sis966/sis966_nic.c
+++ b/src/southbridge/sis/sis966/sis966_nic.c
@@ -124,17 +124,14 @@ static void set_apc(struct device *dev)
     pci_write_config8(dev, 0x73, bTmp);
 }
 
-//-----------------------------------------------------------------------------
-// Procedure:   ReadEEprom
-//
-// Description: This routine serially reads one word out of the EEPROM.
-//
-// Arguments:
-//      Reg - EEPROM word to read.
-//
-// Returns:
-//      Contents of EEPROM word (Reg).
-//-----------------------------------------------------------------------------
+/**
+ * Read one word out of the serial EEPROM.
+ *
+ * @param dev TODO
+ * @param base TODO
+ * @param Reg EEPROM word to read.
+ * @return Contents of EEPROM word (Reg).
+ */
 #define LoopNum 200
 static  unsigned long ReadEEprom( struct device *dev,  u32 base,  u32 Reg)
 {