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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-12 00:25:13 +0200
committerAngel Pons <th3fanbus@gmail.com>2021-01-13 18:30:57 +0000
commitb52784136ee017d17078f9aec6533fd3b1b896c4 (patch)
tree82aec6153313ec369f37d055dc8eb376a427bed8 /src/southbridge
parent84935f7de5d4906d77e4abe76a475eac8592ec6a (diff)
sb/intel: Add CBMC entries in GNVS
While unused, this allows use of a common initialisation code for GNVS allocation. Change-Id: Ie84b5a3e16d3baa12bcd5dadac0b1f7edb323272 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/globalnvs.asl1
-rw-r--r--src/southbridge/intel/bd82x6x/nvs.h4
-rw-r--r--src/southbridge/intel/i82801gx/acpi/globalnvs.asl1
-rw-r--r--src/southbridge/intel/i82801gx/nvs.h4
-rw-r--r--src/southbridge/intel/i82801ix/acpi/globalnvs.asl1
-rw-r--r--src/southbridge/intel/i82801ix/nvs.h4
-rw-r--r--src/southbridge/intel/i82801jx/acpi/globalnvs.asl1
-rw-r--r--src/southbridge/intel/i82801jx/nvs.h4
-rw-r--r--src/southbridge/intel/ibexpeak/acpi/globalnvs.asl1
-rw-r--r--src/southbridge/intel/ibexpeak/nvs.h4
10 files changed, 20 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index ec193c4228..9194f3f5ce 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -110,6 +110,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xf5),
TPIQ, 8, // 0xf5 - trackpad IRQ value
+ CBMC, 32,
/* ChromeOS specific */
Offset (0x100),
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index b75e0ab025..949467b61c 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -100,8 +100,10 @@ struct __packed global_nvs {
/* XHCI */
u8 xhci;
u8 rsvd12[65];
+
u8 tpiq; /* 0xf5 - trackpad IRQ value */
- u8 rsvd13[10]; /* 0xf6 - rsvd */
+ u32 cbmc;
+ u8 rsvd13[6]; /* 0xfa - rsvd */
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index 848005dcb9..9b8fd1187d 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -108,4 +108,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xf0),
DOCK, 8, // 0xf0 - Docking Status
BTEN, 8, // 0xf1 - Bluetooth Enable
+ CBMC, 32,
}
diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h
index d2efc5c8b1..b23b85bec2 100644
--- a/src/southbridge/intel/i82801gx/nvs.h
+++ b/src/southbridge/intel/i82801gx/nvs.h
@@ -96,7 +96,9 @@ struct __packed global_nvs {
/* Mainboard specific */
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
- u8 rsvd13[14];
+
+ u32 cbmc;
+ u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index 5c9e26ea27..5687eb0e0b 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -110,4 +110,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xf0),
DOCK, 8, // 0xf0 - Docking Status
BTEN, 8, // 0xf1 - Bluetooth Enable
+ CBMC, 32,
}
diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h
index e0e6bbd68d..83dd7e508d 100644
--- a/src/southbridge/intel/i82801ix/nvs.h
+++ b/src/southbridge/intel/i82801ix/nvs.h
@@ -96,7 +96,9 @@ struct __packed global_nvs {
/* Mainboard specific */
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
- u8 rsvd13[14];
+
+ u32 cbmc;
+ u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index 5c9e26ea27..5687eb0e0b 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -110,4 +110,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xf0),
DOCK, 8, // 0xf0 - Docking Status
BTEN, 8, // 0xf1 - Bluetooth Enable
+ CBMC, 32,
}
diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h
index 48a7d87fe1..96c0a40e05 100644
--- a/src/southbridge/intel/i82801jx/nvs.h
+++ b/src/southbridge/intel/i82801jx/nvs.h
@@ -95,7 +95,9 @@ struct __packed global_nvs {
/* Mainboard specific */
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
- u8 rsvd13[14];
+
+ u32 cbmc;
+ u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */
diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
index a650a688c1..62e388801c 100644
--- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
+++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
@@ -107,6 +107,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* XHCI */
Offset (0xb2),
XHCI, 8,
+ CBMC, 32,
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
index 799af47090..bc18c2584d 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -98,7 +98,9 @@ struct __packed global_nvs {
u8 rsvd11[6];
/* XHCI */
u8 xhci;
- u8 rsvd13[76]; /* 0xf5 - rsvd */
+
+ u32 cbmc;
+ u8 rsvd13[72]; /* rsvd */
};
#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */