diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-08-30 20:47:13 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-19 21:32:22 +0200 |
| commit | a2d4062d427d18127707306dada5e79d69bd3691 (patch) | |
| tree | bcf9f53b1f1d74c9d04df6d42af2602ff97038b4 /src/southbridge | |
| parent | 21130c6508161ada1d28c90a4003c89afc3fd162 (diff) | |
soc/intel/skylake: Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions