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author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-06-16 23:54:46 -0600 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-18 08:33:03 +0000 |
commit | 8021b474fb83c201e3d8d9fbc82ef8d5d9ac4a54 (patch) | |
tree | e7cbf1002ad703dd018b946e5d3a5935ea2a9322 /src/southbridge | |
parent | 203af604644abc156acac61da3fe8c280639cd3a (diff) |
soc/intel/jasperlake: Enable FSP-S compression
Use LZ4 compression technique to compress FSP-S. This provides some
SPI ROM space savings(~60 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZ4 is chosen over LZMA since the decompression saves
~50 ms for an extra overhead of ~1.5 KiB.
LZ4 Compression:
fsps.bin 0xa9fc0 fsp 203423 LZ4 (262144 decompressed)
LZ4 Decompression:
17:starting LZ4 decompress (ignore for x86) 433,550 (1,154)
18:finished LZ4 decompress (ignore for x86) 461,620 (28,069)
LZMA Compression:
fsps.bin 0xa9fc0 fsp 202132 LZMA (262144 decompressed)
LZMA Decompression:
15:starting LZMA decompress (ignore for x86) 478,448 (1,174)
16:finished LZMA decompress (ignore for x86) 557,725 (79,277)
BUG=b:158034451
TEST=Build and boot waddledoo mainboard.
Change-Id: I416b1d91d7f4836b1e9c641b0fe07b39876364ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions