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authorStefan Reinauer <stepan@openbios.org>2004-02-05 10:00:35 +0000
committerStefan Reinauer <stepan@openbios.org>2004-02-05 10:00:35 +0000
commitbd8e17a8f16846bb35a6a2fd07720a5b087e92d8 (patch)
tree53e15d5d9c75c90211add06fb5de9d338cf53efe /src/southbridge
parentb8a7578a120f70470a733292908b97261e9c518a (diff)
enable hpet timer hardware.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/amd8111/amd8111_lpc.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 437ed2e877..535cbece66 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -86,6 +86,16 @@ static void setup_ioapic(void)
}
}
+static void enable_hpet(struct device *dev)
+{
+ unsigned long hpet_address;
+
+ pci_write_config32(dev,0xa0, 0xfed00001);
+ hpet_address=pci_read_config32(dev,0xa0)& 0xfffffffe;
+ printk_debug("enabling HPET @0x%x\n", hpet_address);
+
+}
+
static void lpc_init(struct device *dev)
{
uint8_t byte;
@@ -117,6 +127,7 @@ static void lpc_init(struct device *dev)
byte |= (1 << 5);
pci_write_config8(dev, 0x41, byte);
+ enable_hpet(dev);
}
static void amd8111_lpc_read_resources(device_t dev)