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authorMichael Niewöhner <foss@mniewoehner.de>2020-08-03 16:53:41 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2021-10-17 17:27:43 +0000
commitf6611a2ea8d9288e57ce08b9190b3e401c18edd5 (patch)
tree57c849731f6f7fbb12fdf5bf08ad054c7136b55d /src/southbridge
parentc9a12f2402bb9151f8a0643d98bb6915bf06531e (diff)
soc/intel/skylake: switch to common ACPI code
Use the common ACPI code to reduce code duplication. After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state table generation (as of commit c2540a9) and the number reduces from 10 to 7 entries. Also, remnants of P_BLK support missed in CB:58096 will vanish. Tested on google/fizz: no errors in dmesg, ACPI tables remain the same (except PSS, as mentioned above). Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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