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authorRobbie Zhang <robbie.zhang@intel.com>2017-02-13 12:07:53 -0800
committerMartin Roth <martinroth@google.com>2017-02-18 06:30:53 +0100
commite65affa2ed5d4fea584532c5cf27bf51ed1f56eb (patch)
treec9a4ec6fa8e87ad482ee693c83603375d1572466 /src/southbridge
parentef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8 (diff)
soc/intel/skylake: add PrmrrSize to chip config
Prmrr configuration is supported by Kabylake FSP-M with UPD provided. It is required as one of the SGX initialization steps in BIOS. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set size and boot. Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18361 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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