diff options
| author | Varshit B Pandya <varshit.b.pandya@intel.com> | 2022-04-02 15:26:23 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-05 14:49:07 +0000 |
| commit | be1a050772a41b9927db2a94fa00874d6f789094 (patch) | |
| tree | 9b9199ca6607be9d7abc05872bb12ba88d0fd9b8 /src/southbridge | |
| parent | 170a76caa7d9080612f6cf9b1374aca295627efb (diff) | |
soc/intel/alderlake: Add HID for DPTF Battery Participant
HID is defined in Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check BAT1 device HID
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions