diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-03-23 22:41:05 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-25 20:06:57 +0000 |
| commit | bbf5de55caebd6814db129e484aeb158fc7eafd5 (patch) | |
| tree | fd0a9e5c4bd7f62f5fec0bd96f396c72454db58b /src/southbridge | |
| parent | f128adda88350a4c394978b4409fda3565d9422e (diff) | |
sb/amd/hudson/spi.c: Use C over CPP conditional
Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/spi.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index b2f9ff2f72..986f094a77 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -97,15 +97,15 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, readoffby1 = bytesout ? 0 : 1; -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - spi_write(0x1E, 5); - spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ - spi_write(0x1E, 6); - spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ -#else - u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; - spi_write(SPI_REG_CNTRL01, readwrite); -#endif + if (CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)) { + spi_write(0x1E, 5); + spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ + spi_write(0x1E, 6); + spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ + } else { + u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; + spi_write(SPI_REG_CNTRL01, readwrite); + } spi_write(SPI_REG_OPCODE, cmd); reset_internal_fifo_pointer(); |