diff options
| author | Keith Hui <buurin@gmail.com> | 2020-05-21 16:57:15 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:08:43 +0000 |
| commit | a5a8e0962a06ad57fbcebb2ec41a4442e392a898 (patch) | |
| tree | bfab7d2a3467f2db67caf4b8518850435596b35c /src/southbridge | |
| parent | 7cf47cfda44ada201937c5801cfe8ff1754a9c9c (diff) | |
sb/intel/i82371eb: Clean up PM register #defines
Remove EIO define. It is unused and means something else,
elsewhere in the tree.
Move PMIOSE bit definition next to PMREGMISC, where it actually
belongs.
Correct a number of bit defines with glaring errors.
Clarify in comments which PM register defines are in PCI config
space are which are in I/O space.
Change-Id: Ic7f2267d013403c0a519c2ee1786bd3c7f5a9708
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index e20cb5f1fb..405bb74160 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -39,7 +39,7 @@ void i82371eb_early_init(void); #define SMBUS_IO_BASE 0x0f00 #define SMBHSTCFG 0xd2 /* SMBus host configuration */ -/* Power management (ACPI) */ +/* Power management (ACPI) I/O ports, offset from PM_IO_BASE below */ #define PMSTS 0x00 /* Power Management Status */ #define PMEN 0x02 /* Power Management Resume Enable */ #define PWRBTN_EN (1<<8) @@ -49,8 +49,7 @@ void i82371eb_early_init(void); #define SUS_TYP_MSK (7<<10) #define SUS_TYP_S0 (5<<10) #define SUS_TYP_S1 (4<<10) -#define SUS_TYP_S2 (3<<10) -//#define SUS_TYP_S2>---(2<<10) +#define SUS_TYP_S2 (3<<10) /* S2 may also map as 2<<10 */ #define SUS_TYP_S3 (1<<10) #define SUS_TYP_S5 (0<<10) #define SCI_EN (1<<0) @@ -64,11 +63,11 @@ void i82371eb_early_init(void); #define EXTSMI_STS (1<<10) #define GSTBY_STS (1<<8) #define GP_STS (1<<7) -#define BM1_STS (1<<6) +#define PM1_STS (1<<6) #define APM_STS (1<<5) #define DEV_STS (1<<4) -#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ -#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define LEGACY_USB_STS (1<<1) +#define BIOS_STS (1<<0) #define DEVSTS 0x1c /* Device Status */ #define GLBEN 0x20 /* Global Enable */ #define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ @@ -86,10 +85,12 @@ void i82371eb_early_init(void); #define GPO2 0x36 #define GPO3 0x37 +/* Power management (ACPI) PCI registers */ #define PMBA 0x40 /* Power management base address */ #define DEFAULT_PMBASE 0xe400 #define PM_IO_BASE DEFAULT_PMBASE #define PMREGMISC 0x80 /* Miscellaneous power management */ +#define PMIOSE (1 << 0) /* PM I/O Space Enable */ /* Bit definitions */ #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ @@ -105,7 +106,5 @@ void i82371eb_early_init(void); #define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ #define ISA (1 << 0) /* Select ISA */ -#define EIO (0 << 0) /* Select EIO */ -#define PMIOSE (1 << 0) /* PM I/O Space Enable */ #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ |