diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-02 12:13:23 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-18 10:10:13 +0000 |
| commit | 9b629ad37f2fa9ceda61e2b18bc53f69833235c1 (patch) | |
| tree | b411a5ba092de22f158fe7bb2943e9d67d6a0759 /src/southbridge | |
| parent | ea9c96aa9cc41234c99092ed13b536f6cb77ce22 (diff) | |
sb/intel/lynxpoint: Correct read width in RMW cycle
The register is 32 bits wide, so do not read 16 bits out of it.
LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses.
Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/sata.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 33a048d9cf..2a356004aa 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -74,7 +74,7 @@ static void sata_init(struct device *dev) udelay(2); /* Setup register 98h */ - reg32 = pci_read_config16(dev, 0x98); + reg32 = pci_read_config32(dev, 0x98); reg32 |= 1 << 19; /* BWG step 6 */ reg32 |= 1 << 22; /* BWG step 5 */ reg32 &= ~(0x3f << 7); |