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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-31 21:48:48 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-09 11:41:34 +0100 |
| commit | cd02ef19e5b26abf2b35a47b31f31e0cde3a9820 (patch) | |
| tree | 80be52653733c94c221e37802c32af0baad856b3 /src/southbridge | |
| parent | 29d358e6a1773205fb225f380e1a1d052912abfe (diff) | |
Intel FSP platforms: Fix timestamps
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR.
Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb68c2..a668815fe8 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -53,6 +53,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) */ outb(0x40, 0x80); + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Rangeley UART POR state is enabled */ console_init(); post_code(0x41); @@ -75,6 +78,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) read32(func_dis); } + timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -94,9 +99,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - uint64_t after_initram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); post_code(0x48); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", @@ -127,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); post_code(0x4f); |