amdfam10: Remove use of __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

18 files changed, 39 insertions, 45 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h
index a984143a17..447edf9b4c 100644
--- a/src/southbridge/amd/amd8111/amd8111.h
+++ b/src/southbridge/amd/amd8111/amd8111.h
@@ -14,14 +14,9 @@
 #ifndef AMD8111_H
 #define AMD8111_H
 
-#include "chip.h"
+#include <device/device.h>
 
-#ifndef __SIMPLE_DEVICE__
 void amd8111_enable(struct device *dev);
-#endif
-
-#ifdef __PRE_RAM__
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif
 
 #endif /* AMD8111_H */
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
index 420e28e157..49f9d154f8 100644
--- a/src/southbridge/amd/amd8111/ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
@@ -17,6 +17,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "amd8111.h"
+#include "chip.h"
 
 static void ide_init(struct device *dev)
 {
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index adf8af0d43..a4abd0360a 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -21,7 +21,7 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include "amd8111.h"
-
+#include "chip.h"
 
 #define CMD3		0x54
 
diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c
index 0b11db3c86..070ee67d9c 100644
--- a/src/southbridge/amd/sb700/ide.c
+++ b/src/southbridge/amd/sb700/ide.c
@@ -22,6 +22,7 @@
 #include <types.h>
 
 #include "sb700.h"
+#include "chip.h"
 
 static void ide_init(struct device *dev)
 {
diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c
index 1836f34eb0..1eaf347dcc 100644
--- a/src/southbridge/amd/sb700/sb700.c
+++ b/src/southbridge/amd/sb700/sb700.c
@@ -22,6 +22,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "sb700.h"
+#include "chip.h"
 
 static struct device *find_sm_dev(struct device *dev, u32 devfn)
 {
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 156522e579..4b863a0778 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -17,7 +17,8 @@
 #ifndef SB700_H
 #define SB700_H
 
-#include "chip.h"
+#include <types.h>
+#include <device/device.h>
 
 /* Power management index/data registers */
 #define BIOSRAM_INDEX	0xcd4
@@ -37,14 +38,12 @@
 #define ACPI_CPU_CONTROL	(SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */
 #define ACPI_CPU_P_LVL2		(ACPI_CPU_CONTROL + 0x4)    /* 1 byte */
 
-extern void pm_iowrite(u8 reg, u8 value);
-extern u8 pm_ioread(u8 reg);
-extern void pm2_iowrite(u8 reg, u8 value);
-extern u8 pm2_ioread(u8 reg);
-#ifndef __SIMPLE_DEVICE__
-extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask,
-			       u32 val);
-#endif
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
 
 #define REV_SB700_A11	0x11
 #define REV_SB700_A12	0x12
@@ -58,11 +57,7 @@ extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask,
  * The differentiate is 0x28, isn't it? */
 #define get_sb700_revision(sm_dev)	(pci_read_config8((sm_dev), 0x08) - 0x28)
 
-#ifndef __SIMPLE_DEVICE__
-void sb7xx_51xx_enable(struct device *dev);
-#endif
 
-#ifdef __PRE_RAM__
 void sb7xx_51xx_lpc_port80(void);
 void sb7xx_51xx_pci_port80(void);
 void sb7xx_51xx_lpc_init(void);
@@ -71,14 +66,12 @@ void sb7xx_51xx_disable_wideio(u8 wio_index);
 void sb7xx_51xx_early_setup(void);
 void sb7xx_51xx_before_pci_init(void);
 uint16_t sb7xx_51xx_decode_last_reset(void);
-#else
-#include <device/pci.h>
-#include <device/pci_ops.h>
+
+
 /* allow override in mainboard.c */
 void sb7xx_51xx_setup_sata_phys(struct device *dev);
 void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5);
-
-#endif
+void sb7xx_51xx_enable(struct device *dev);
 
 void set_lpc_sticky_ctl(bool enable);
 
@@ -86,4 +79,5 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
 void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
+
 #endif /* SB700_H */
diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c
index fddb48c8d2..77e2f5ef1d 100644
--- a/src/southbridge/amd/sb800/ide.c
+++ b/src/southbridge/amd/sb800/ide.c
@@ -18,6 +18,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "sb800.h"
+#include "chip.h"
 
 static void ide_init(struct device *dev)
 {
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index 48a8740122..8611272d78 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -22,6 +22,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include "sb800.h"
+#include "chip.h"
 
 static int sata_drive_detect(int portnum, u16 iobar)
 {
diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c
index 801cc65e4a..c7efaec732 100644
--- a/src/southbridge/amd/sb800/sb800.c
+++ b/src/southbridge/amd/sb800/sb800.c
@@ -23,6 +23,7 @@
 #include <device/pci_ops.h>
 #include "sb800.h"
 #include "smbus.h"
+#include "chip.h"
 
 static struct device *find_sm_dev(struct device *dev, u32 devfn)
 {
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index 3715a3ac1c..07c78ec429 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -17,7 +17,8 @@
 #ifndef SB800_H
 #define SB800_H
 
-#include "chip.h"
+#include <types.h>
+#include <device/device.h>
 
 /* Power management index/data registers */
 #define BIOSRAM_INDEX	0xcd4
@@ -42,15 +43,11 @@ u8 pm_ioread(u8 reg);
 void pm2_iowrite(u8 reg, u8 value);
 u8 pm2_ioread(u8 reg);
 
-#ifndef __SIMPLE_DEVICE__
 void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
-#endif
 
 #define REV_SB800_A11	0x11
 #define REV_SB800_A12	0x12
 
-
-#ifdef __PRE_RAM__
 void sb800_lpc_port80(void);
 void sb800_pci_port80(void);
 void sb800_clk_output_48Mhz(void);
@@ -58,8 +55,6 @@ void sb800_clk_output_48Mhz(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-#else
 void sb800_enable(struct device *dev);
-#endif
 
 #endif /* SB800_H */
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h
index 4517ddad0c..e1c6f66191 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.h
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.h
@@ -20,11 +20,8 @@
 #include <device/device.h>
 #include "chip.h"
 
-#ifndef __PRE_RAM__
 void bcm5785_enable(struct device *dev);
-#else
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif
 
 void bcm5785_set_subsystem(struct device *dev, unsigned int vendor,
 			       unsigned int device);
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index 5505691d1c..6812b5b653 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -26,8 +26,6 @@
 #define CK804B_BUSN 0x80
 #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
 
-#ifdef __PRE_RAM__
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif
 
 #endif
diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h
index cec62b3f49..bf0ff3c719 100644
--- a/src/southbridge/nvidia/ck804/smbus.h
+++ b/src/southbridge/nvidia/ck804/smbus.h
@@ -49,7 +49,9 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	return -3;
 }
 
-#ifndef __PRE_RAM__
+
+/* Platform has severe issues placing non-inlined functions in headers. */
+#if ENV_RAMSTAGE
 static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
 	unsigned char global_status_register, byte;
@@ -114,7 +116,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
 
 	return 0;
 }
-#endif
+#endif /* ENV_RAMSTAGE */
 
 static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
 			      unsigned address)
diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h
index adf47252db..4bc8428a1a 100644
--- a/src/southbridge/nvidia/mcp55/chip.h
+++ b/src/southbridge/nvidia/mcp55/chip.h
@@ -18,8 +18,6 @@
 #ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
 #define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
 
-#include <device/device.h>
-
 struct southbridge_nvidia_mcp55_config
 {
 	unsigned int ide0_enable : 1;
diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c
index 797b9d8780..36e20b4aa0 100644
--- a/src/southbridge/nvidia/mcp55/ide.c
+++ b/src/southbridge/nvidia/mcp55/ide.c
@@ -22,6 +22,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+
+#include "chip.h"
 #include "mcp55.h"
 
 static void ide_init(struct device *dev)
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 8d595c952f..ac689094ca 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -24,13 +24,17 @@
 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#ifndef __PRE_RAM__
-#include "chip.h"
+#ifndef __ROMCC__
+#include <device/device.h>
 void mcp55_enable(struct device *dev);
 extern struct pci_operations mcp55_pci_ops;
-#else
+#endif
+
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
 void enable_smbus(void);
+
+/* Concflict declarations with <device/smbus.h>. */
+#if !ENV_RAMSTAGE
 int smbus_recv_byte(unsigned device);
 int smbus_send_byte(unsigned device, unsigned char val);
 int smbus_read_byte(unsigned device, unsigned address);
@@ -40,6 +44,6 @@ int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val);
 int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
 int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
 		unsigned char val);
-#endif
+#endif /* !ENV_RAMSTAGE */
 
 #endif
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index 4ee3a3b79a..af4df44293 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -25,6 +25,8 @@
 #include <device/pci_ops.h>
 #include <device/mmio.h>
 #include <delay.h>
+
+#include "chip.h"
 #include "mcp55.h"
 
 static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c
index 27f60738b3..9f70890ff7 100644
--- a/src/southbridge/nvidia/mcp55/sata.c
+++ b/src/southbridge/nvidia/mcp55/sata.c
@@ -23,6 +23,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
+#include "chip.h"
 #include "mcp55.h"
 
 static void sata_init(struct device *dev)