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authorRonald G. Minnich <rminnich@gmail.com>2003-10-02 22:48:28 +0000
committerRonald G. Minnich <rminnich@gmail.com>2003-10-02 22:48:28 +0000
commita70483b83bdc733e187ca6955b4edfa02a4d80e0 (patch)
treed07fe2c2d5f1e7369ac541671d1ab9a28b0890ef /src/southbridge
parentcb3f498296bad22b360796139bc454d141d7ccc9 (diff)
First SPD code in and working!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/via/vt8231/vt8231_early_smbus.c16
1 files changed, 10 insertions, 6 deletions
diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
index 651f715413..49b942cb23 100644
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -41,10 +41,14 @@ static void enable_smbus(void)
c |= 5;
pci_write_config8(dev, 0xd2, c);
- c = pci_read_config8(dev, 0x54);
- c &= ~0x80;
- pci_write_config8(dev, 0xd2, c);
-
+ /* make it work for I/O ...
+ */
+ dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
+ c = pci_read_config8(dev, 4);
+ c |= 1;
+ pci_write_config8(dev, 4, c);
+ print_err_hex8(c);
+ print_err(" is the comm register\n");
print_debug("SMBus controller enabled\r\n");
}
@@ -139,11 +143,11 @@ static unsigned char smbus_read_byte(unsigned char devAdr,
{
unsigned short i;
unsigned char bData;
- unsigned char sts;
+ unsigned char sts = 0;
/* clear host status */
outb(0xff, SMBUS_IO_BASE);
-
+
/* check SMBUS ready */
for ( i = 0; i < 0xFFFF; i++ )
if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )