devicetree: Change scan_bus() prototype in device ops

The input/output value max is no longer used for tracking the
bus enumeration sequence, everything is handled in the context
of devicetree bus objects.

Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8541
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

6 files changed, 13 insertions, 18 deletions

diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c
index cb76980555..158726818a 100644
--- a/src/southbridge/amd/amd8131/bridge.c
+++ b/src/southbridge/amd/amd8131/bridge.c
@@ -265,9 +265,9 @@ static void amd8131_scan_bus(struct bus *bus,
 	}
 }
 
-static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max)
+static void amd8131_scan_bridge(device_t dev)
 {
-	return do_pci_scan_bridge(dev, max, amd8131_scan_bus);
+	do_pci_scan_bridge(dev, amd8131_scan_bus);
 }
 
 
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 48d7c5168c..027a085bbc 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -194,9 +194,9 @@ static void amd8132_scan_bus(struct bus *bus,
 	amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info);
 }
 
-static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)
+static void amd8132_scan_bridge(device_t dev)
 {
-	return do_pci_scan_bridge(dev, max, amd8132_scan_bus);
+	do_pci_scan_bridge(dev, amd8132_scan_bus);
 }
 
 
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index cece16ddbc..67eabb07ae 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -688,10 +688,10 @@ static struct smbus_bus_operations lops_smbus_bus = {
 	.read_byte  = lsmbus_read_byte,
 };
 
-static unsigned int scan_lpc_smbus(device_t dev, unsigned int max)
+static void scan_lpc_smbus(device_t dev)
 {
 	/* FIXME. Do we have mixed LPC/SMBus device node here. */
-	return scan_smbus(dev, max);
+	scan_smbus(dev);
 }
 
 static struct device_operations southbridge_ops = {
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 42a8578b1d..1b8ac76126 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -273,13 +273,12 @@ static void pch_pcie_enable(device_t dev)
 	pch_pcie_pm_early(dev);
 }
 
-static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
+static void pch_pciexp_scan_bridge(device_t dev)
 {
-	unsigned int ret;
 	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 
 	/* Normal PCIe Scan */
-	ret = pciexp_scan_bridge(dev, max);
+	pciexp_scan_bridge(dev);
 
 	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
 		intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
@@ -287,8 +286,6 @@ static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
 
 	/* Late Power Management init after bridge device enumeration */
 	pch_pcie_pm_late(dev);
-
-	return ret;
 }
 
 static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c
index 815c0812d4..41e921c6f5 100644
--- a/src/southbridge/intel/i3100/pciexp_portb.c
+++ b/src/southbridge/intel/i3100/pciexp_portb.c
@@ -39,7 +39,7 @@ static void pcie_init(struct device *dev)
 {
 }
 
-static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
+static void pcie_scan_bridge(struct device *dev)
 {
 	u16 val;
 	u16 ctl;
@@ -56,7 +56,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
 			hard_reset();
 		}
 	} while	(val & (3<<10));
-	return pciexp_scan_bridge(dev, max);
+
+	pciexp_scan_bridge(dev);
 }
 
 static struct device_operations pcie_ops  = {
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 58c0e19c85..5858176baa 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -110,19 +110,16 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
-static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
+static void pch_pciexp_scan_bridge(device_t dev)
 {
-	unsigned int ret;
 	struct southbridge_intel_i82801ix_config *config = dev->chip_info;
 
 	/* Normal PCIe Scan */
-	ret = pciexp_scan_bridge(dev, max);
+	pciexp_scan_bridge(dev);
 
 	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
 		intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
 	}
-
-	return ret;
 }
 
 static struct pci_operations pci_ops = {