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| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-10-07 13:18:55 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:36:02 +0000 |
| commit | 1aeccd1440bad190f82b5e12b1057680ffd206c3 (patch) | |
| tree | f5395ccd5e604ceb2c9ca813573217f5c9df640a /src/southbridge | |
| parent | 54e1f59215f3adb6ab1f2e8f2413a71ae7a545c2 (diff) | |
sb/intel/lynxpoint/pcie.c: fix typo in comment
Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 2da14ed5f0..0ede943ceb 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -659,7 +659,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set Invalid Recieve Range Check Enable in MPC register. */ + /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25); pci_and_config8(dev, 0xf5, 0x3f); |