Auto-declare chip_operations

The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

38 files changed, 0 insertions, 72 deletions

diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h
index 7732f6d2fe..1970608978 100644
--- a/src/southbridge/amd/agesa/hudson/chip.h
+++ b/src/southbridge/amd/agesa/hudson/chip.h
@@ -30,7 +30,5 @@ struct southbridge_amd_agesa_hudson_config
 	u8  gpp_configuration;
 	#endif
 };
-struct chip_operations;
-extern struct chip_operations southbridge_amd_agesa_hudson_ops;
 
 #endif /* HUDSON_CHIP_H */
diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h
index 601038c441..622bf10fb7 100644
--- a/src/southbridge/amd/amd8111/chip.h
+++ b/src/southbridge/amd/amd8111/chip.h
@@ -8,7 +8,4 @@ struct southbridge_amd_amd8111_config
 	unsigned int phy_lowreset : 1;
 };
 
-struct chip_operations;
-extern struct chip_operations southbridge_amd_amd8111_ops;
-
 #endif /* AMD8111_CHIP_H */
diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h
index ef294f450c..05edc5c288 100644
--- a/src/southbridge/amd/cimx/sb700/chip.h
+++ b/src/southbridge/amd/cimx/sb700/chip.h
@@ -20,8 +20,6 @@
 #ifndef _CIMX_SB700_CHIP_H_
 #define _CIMX_SB700_CHIP_H_
 
-extern struct chip_operations southbridge_amd_cimx_sb700_ops;
-
 /*
  * configuration set in mainboard/devicetree.cb
  *  boot_switch_sata_ide:
diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h
index 3581f2e3b0..7fc7b88c76 100644
--- a/src/southbridge/amd/cimx/sb800/chip.h
+++ b/src/southbridge/amd/cimx/sb800/chip.h
@@ -20,8 +20,6 @@
 #ifndef _CIMX_SB800_CHIP_H_
 #define _CIMX_SB800_CHIP_H_
 
-extern struct chip_operations southbridge_amd_cimx_sb800_ops;
-
 /*
  * configuration set in mainboard/devicetree.cb
  *  boot_switch_sata_ide:
diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h
index 96afc42736..9004969b85 100644
--- a/src/southbridge/amd/cimx/sb900/chip.h
+++ b/src/southbridge/amd/cimx/sb900/chip.h
@@ -20,8 +20,6 @@
 #ifndef _CIMX_SB900_CHIP_H_
 #define _CIMX_SB900_CHIP_H_
 
-extern struct chip_operations southbridge_amd_cimx_sb900_ops;
-
 /*
  * configuration set in mainboard/devicetree.cb
  *  boot_switch_sata_ide:
diff --git a/src/southbridge/amd/cs5530/chip.h b/src/southbridge/amd/cs5530/chip.h
index 92d64e49f9..271facb147 100644
--- a/src/southbridge/amd/cs5530/chip.h
+++ b/src/southbridge/amd/cs5530/chip.h
@@ -21,8 +21,6 @@
 #ifndef SOUTHBRIDGE_AMD_CS5530_CHIP_H
 #define SOUTHBRIDGE_AMD_CS5530_CHIP_H
 
-extern struct chip_operations southbridge_amd_cs5530_ops;
-
 struct southbridge_amd_cs5530_config {
 	int ide0_enable:1;
 	int ide1_enable:1;
diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h
index 3894a06906..d4dde3d6ee 100644
--- a/src/southbridge/amd/cs5535/chip.h
+++ b/src/southbridge/amd/cs5535/chip.h
@@ -1,8 +1,6 @@
 #ifndef _SOUTHBRIDGE_AMD_CS5535
 #define _SOUTHBRIDGE_AMD_CS5535
 
-extern struct chip_operations southbridge_amd_cs5535_ops;
-
 struct southbridge_amd_cs5535_config {
 	int setupflash;
 };
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h
index ad9e736dec..69deadc70b 100644
--- a/src/southbridge/amd/cs5536/chip.h
+++ b/src/southbridge/amd/cs5536/chip.h
@@ -23,8 +23,6 @@
 
 #define MAX_UNWANTED_VPCI 8	/* increase if needed */
 
-extern struct chip_operations southbridge_amd_cs5536_ops;
-
 struct southbridge_amd_cs5536_config {
 	unsigned int lpc_serirq_enable;	/* interrupt enables for LPC bus; each bit is an irq 0-15 */
 	unsigned int lpc_serirq_polarity;	/* LPC IRQ polarity; each bit is an irq 0-15 */
diff --git a/src/southbridge/amd/rs690/chip.h b/src/southbridge/amd/rs690/chip.h
index 5e08cc59f8..8ff4be5401 100644
--- a/src/southbridge/amd/rs690/chip.h
+++ b/src/southbridge/amd/rs690/chip.h
@@ -33,7 +33,5 @@ struct southbridge_amd_rs690_config
 	u8 gfx_reconfiguration;	/* Dynamic Lind Width Control */
 	u8 gfx_link_width;	/* Desired width of lane 2 */
 };
-struct chip_operations;
-extern struct chip_operations southbridge_amd_rs690_ops;
 
 #endif /* RS690_CHIP_H */
diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h
index 4a10ae0f8a..7afcbf2236 100644
--- a/src/southbridge/amd/rs780/chip.h
+++ b/src/southbridge/amd/rs780/chip.h
@@ -36,7 +36,5 @@ struct southbridge_amd_rs780_config
 	u8 gfx_pcie_config;		/* GFX PCIE Modes */
 	u8 gfx_ddi_config;		/* GFX DDI Modes */
 };
-struct chip_operations;
-extern struct chip_operations southbridge_amd_rs780_ops;
 
 #endif /* RS780_CHIP_H */
diff --git a/src/southbridge/amd/sb600/chip.h b/src/southbridge/amd/sb600/chip.h
index ce40f18bf3..e288cbff89 100644
--- a/src/southbridge/amd/sb600/chip.h
+++ b/src/southbridge/amd/sb600/chip.h
@@ -24,7 +24,5 @@ struct southbridge_amd_sb600_config
 {
 	u32 hda_viddid;
 };
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sb600_ops;
 
 #endif /* SB600_CHIP_H */
diff --git a/src/southbridge/amd/sb700/chip.h b/src/southbridge/amd/sb700/chip.h
index acdb2b712c..390c579e52 100644
--- a/src/southbridge/amd/sb700/chip.h
+++ b/src/southbridge/amd/sb700/chip.h
@@ -24,7 +24,5 @@ struct southbridge_amd_sb700_config
 {
 	u32 boot_switch_sata_ide : 1;
 };
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sb700_ops;
 
 #endif /* SB700_CHIP_H */
diff --git a/src/southbridge/amd/sb800/chip.h b/src/southbridge/amd/sb800/chip.h
index 41f26d16c0..13e1aacd72 100644
--- a/src/southbridge/amd/sb800/chip.h
+++ b/src/southbridge/amd/sb800/chip.h
@@ -28,7 +28,5 @@ struct southbridge_amd_sb800_config
 	u32 hda_viddid;
 	u8  gpp_configuration;
 };
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sb800_ops;
 
 #endif /* SB800_CHIP_H */
diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h
index 43f8dd343c..236ac16b3e 100644
--- a/src/southbridge/amd/sr5650/chip.h
+++ b/src/southbridge/amd/sr5650/chip.h
@@ -28,7 +28,5 @@ struct southbridge_amd_sr5650_config
 	u8 gpp3a_configuration;		/* The configuration of General Purpose Port. */
 	u16 port_enable;		/* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */
 };
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sr5650_ops;
 
 #endif /* SR5650_CHIP_H */
diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h
index eb337e9624..d323bee6c4 100644
--- a/src/southbridge/broadcom/bcm5785/chip.h
+++ b/src/southbridge/broadcom/bcm5785/chip.h
@@ -28,7 +28,5 @@ struct southbridge_broadcom_bcm5785_config
         unsigned int sata0_enable : 1;
         unsigned int sata1_enable : 1;
 };
-struct chip_operations;
-extern struct chip_operations southbridge_broadcom_bcm5785_ops;
 
 #endif /* BCM5785_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 07a2af7b9c..05eeab225d 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -79,6 +79,4 @@ struct southbridge_intel_bd82x6x_config {
 	uint8_t pcie_port_coalesce;
 };
 
-extern struct chip_operations southbridge_intel_bd82x6x_ops;
-
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h
index 4082769cce..c6dc3a36ee 100644
--- a/src/southbridge/intel/esb6300/chip.h
+++ b/src/southbridge/intel/esb6300/chip.h
@@ -26,5 +26,4 @@ struct southbridge_intel_esb6300_config
 	unsigned int  pirq_a_d;
 	unsigned int  pirq_e_h;
 };
-extern struct chip_operations southbridge_intel_esb6300_ops;
 
diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h
index 7e58674daf..21d3a46591 100644
--- a/src/southbridge/intel/i3100/chip.h
+++ b/src/southbridge/intel/i3100/chip.h
@@ -47,4 +47,3 @@ struct southbridge_intel_i3100_config
 	u32 pirq_a_d;
 	u32 pirq_e_h;
 };
-extern struct chip_operations southbridge_intel_i3100_ops;
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 1cb2929346..80846930c5 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -23,8 +23,6 @@
 
 #include <device/device.h>
 
-extern const struct chip_operations southbridge_intel_i82371eb_ops;
-
 struct southbridge_intel_i82371eb_config {
 	int ide0_enable:1;
 	int ide0_drive0_udma33_enable:1;
diff --git a/src/southbridge/intel/i82801ax/chip.h b/src/southbridge/intel/i82801ax/chip.h
index 21b6f9fcf3..989f35b917 100644
--- a/src/southbridge/intel/i82801ax/chip.h
+++ b/src/southbridge/intel/i82801ax/chip.h
@@ -37,6 +37,4 @@ struct southbridge_intel_i82801ax_config {
 	u8 ide1_enable;
 };
 
-extern struct chip_operations southbridge_intel_i82801ax_ops;
-
 #endif
diff --git a/src/southbridge/intel/i82801bx/chip.h b/src/southbridge/intel/i82801bx/chip.h
index 5cdfc5da50..987eb8f8b2 100644
--- a/src/southbridge/intel/i82801bx/chip.h
+++ b/src/southbridge/intel/i82801bx/chip.h
@@ -41,6 +41,4 @@ struct southbridge_intel_i82801bx_config {
 	u8 ide1_enable;
 };
 
-extern struct chip_operations southbridge_intel_i82801bx_ops;
-
 #endif
diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h
index 88415e0556..56185213eb 100644
--- a/src/southbridge/intel/i82801cx/chip.h
+++ b/src/southbridge/intel/i82801cx/chip.h
@@ -4,6 +4,5 @@
 struct southbridge_intel_i82801cx_config
 {
 };
-extern struct chip_operations southbridge_intel_i82801cx_ops;
 
 #endif /* I82801CX_CHIP_H */
diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h
index 1209ec854b..42701f778f 100644
--- a/src/southbridge/intel/i82801dx/chip.h
+++ b/src/southbridge/intel/i82801dx/chip.h
@@ -41,6 +41,4 @@ struct southbridge_intel_i82801dx_config {
 	uint8_t ide1_enable;
 };
 
-extern struct chip_operations southbridge_intel_i82801dx_ops;
-
 #endif				/* I82801DBM_CHIP_H */
diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h
index f04fc3fd29..891fa16d15 100644
--- a/src/southbridge/intel/i82801ex/chip.h
+++ b/src/southbridge/intel/i82801ex/chip.h
@@ -30,7 +30,6 @@ struct southbridge_intel_i82801ex_config
 	unsigned int  pirq_a_d;
 	unsigned int  pirq_e_h;
 };
-extern struct chip_operations southbridge_intel_i82801ex_ops;
 
 #endif /* I82801EX_CHIP_H */
 
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index cc17539d7d..5e4408aebf 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -73,6 +73,4 @@ struct southbridge_intel_i82801gx_config {
 	int c4onc3_enable:1;
 };
 
-extern struct chip_operations southbridge_intel_i82801gx_ops;
-
 #endif				/* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */
diff --git a/src/southbridge/intel/pxhd/chip.h b/src/southbridge/intel/pxhd/chip.h
index 5aedb77776..27d88a8277 100644
--- a/src/southbridge/intel/pxhd/chip.h
+++ b/src/southbridge/intel/pxhd/chip.h
@@ -3,4 +3,3 @@ struct southbridge_intel_pxhd_config
 	/* nothing */
 };
 
-extern struct chip_operations southbridge_intel_pxhd_ops;
diff --git a/src/southbridge/intel/sch/chip.h b/src/southbridge/intel/sch/chip.h
index 116d382768..1ae5c32e0c 100644
--- a/src/southbridge/intel/sch/chip.h
+++ b/src/southbridge/intel/sch/chip.h
@@ -35,6 +35,4 @@ struct southbridge_intel_sch_config {
 	uint8_t pirqh_routing;
 };
 
-extern struct chip_operations southbridge_intel_sch_ops;
-
 #endif
diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h
index 1730205581..64d42254af 100644
--- a/src/southbridge/nvidia/ck804/chip.h
+++ b/src/southbridge/nvidia/ck804/chip.h
@@ -30,7 +30,5 @@ struct southbridge_nvidia_ck804_config {
 	unsigned int mac_eeprom_smbus;
 	unsigned int mac_eeprom_addr;
 };
-struct chip_operations;
-extern struct chip_operations southbridge_nvidia_ck804_ops;
 
 #endif
diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h
index 00fd0829a3..bfcd1e9e41 100644
--- a/src/southbridge/nvidia/mcp55/chip.h
+++ b/src/southbridge/nvidia/mcp55/chip.h
@@ -33,7 +33,5 @@ struct southbridge_nvidia_mcp55_config
 	unsigned int mac_eeprom_smbus;
 	unsigned int mac_eeprom_addr;
 };
-struct chip_operations;
-extern struct chip_operations southbridge_nvidia_mcp55_ops;
 
 #endif
diff --git a/src/southbridge/ricoh/rl5c476/chip.h b/src/southbridge/ricoh/rl5c476/chip.h
index 922eece219..98d8a6936d 100644
--- a/src/southbridge/ricoh/rl5c476/chip.h
+++ b/src/southbridge/ricoh/rl5c476/chip.h
@@ -1,8 +1,6 @@
 #ifndef _SOUTHBRIDGE_RICOH_RL5C476
 #define _SOUTHBRIDGE_RICOH_RL5C476
 
-extern struct chip_operations southbridge_ricoh_rl5c476_ops;
-
 struct southbridge_ricoh_rl5c476_config {
 	int enable_cf;
 };
diff --git a/src/southbridge/sis/sis966/chip.h b/src/southbridge/sis/sis966/chip.h
index c169bb50cc..3669f3bae9 100644
--- a/src/southbridge/sis/sis966/chip.h
+++ b/src/southbridge/sis/sis966/chip.h
@@ -31,7 +31,5 @@ struct southbridge_sis_sis966_config
 	unsigned int mac_eeprom_smbus;
 	unsigned int mac_eeprom_addr;
 };
-struct chip_operations;
-extern struct chip_operations southbridge_sis_sis966_ops;
 
 #endif /* SIS966_CHIP_H */
diff --git a/src/southbridge/ti/pci1x2x/chip.h b/src/southbridge/ti/pci1x2x/chip.h
index 4c3676153d..2dbb1aab0d 100644
--- a/src/southbridge/ti/pci1x2x/chip.h
+++ b/src/southbridge/ti/pci1x2x/chip.h
@@ -1,8 +1,6 @@
 #ifndef SOUTHBRIDGE_TI_PCI1X2X_H
 #define SOUTHBRIDGE_TI_PCI1X2X_H
 
-extern struct chip_operations southbridge_ti_pci1x2x_ops;
-
 struct southbridge_ti_pci1x2x_config {
 	int scr;
 	int mrr;
diff --git a/src/southbridge/ti/pci7420/chip.h b/src/southbridge/ti/pci7420/chip.h
index d7ec2da410..cc218a12c9 100644
--- a/src/southbridge/ti/pci7420/chip.h
+++ b/src/southbridge/ti/pci7420/chip.h
@@ -21,8 +21,6 @@
 #ifndef _SOUTHBRIDGE_TI_PCI7420
 #define _SOUTHBRIDGE_TI_PCI7420
 
-extern struct chip_operations southbridge_ti_pci7420_ops;
-
 struct southbridge_ti_pci7420_config {
 	int smartcard_enabled;
 };
diff --git a/src/southbridge/ti/pcixx12/chip.h b/src/southbridge/ti/pcixx12/chip.h
index 42dc79cd1a..03151a8916 100644
--- a/src/southbridge/ti/pcixx12/chip.h
+++ b/src/southbridge/ti/pcixx12/chip.h
@@ -20,8 +20,6 @@
 #ifndef _SOUTHBRIDGE_TI_PCIXX12
 #define _SOUTHBRIDGE_TI_PCIXX12
 
-extern struct chip_operations southbridge_ti_pcixx12_ops;
-
 struct southbridge_ti_pcixx12_config {
 	int dummy;
 
diff --git a/src/southbridge/via/vt8231/chip.h b/src/southbridge/via/vt8231/chip.h
index 277ead7705..e858ff5086 100644
--- a/src/southbridge/via/vt8231/chip.h
+++ b/src/southbridge/via/vt8231/chip.h
@@ -1,8 +1,6 @@
 #ifndef _SOUTHBRIDGE_VIA_VT8231
 #define _SOUTHBRIDGE_VIA_VT8231
 
-extern struct chip_operations southbridge_via_vt8231_ops;
-
 struct southbridge_via_vt8231_config {
 	/* enables of Non-PCI devices */
 	int enable_native_ide;
diff --git a/src/southbridge/via/vt8235/chip.h b/src/southbridge/via/vt8235/chip.h
index 50f4a85547..eb1e82b7c8 100644
--- a/src/southbridge/via/vt8235/chip.h
+++ b/src/southbridge/via/vt8235/chip.h
@@ -1,8 +1,6 @@
 #ifndef _SOUTHBRIDGE_VIA_VT8235
 #define _SOUTHBRIDGE_VIA_VT8235
 
-extern struct chip_operations southbridge_via_vt8235_ops;
-
 struct southbridge_via_vt8235_config {
 	/* PCI function enables */
 	/* i.e. so that pci scan bus will find them. */
diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h
index 510854716a..cbc795271a 100644
--- a/src/southbridge/via/vt8237r/chip.h
+++ b/src/southbridge/via/vt8237r/chip.h
@@ -22,8 +22,6 @@
 
 #include <stdint.h>
 
-extern struct chip_operations southbridge_via_vt8237r_ops;
-
 struct southbridge_via_vt8237r_config {
 	/**
 	 * Function disable. 1 = disabled.
diff --git a/src/southbridge/via/vt82c686/chip.h b/src/southbridge/via/vt82c686/chip.h
index 8effc737e4..44b3e2dfa1 100644
--- a/src/southbridge/via/vt82c686/chip.h
+++ b/src/southbridge/via/vt82c686/chip.h
@@ -25,8 +25,6 @@
 #include <pc80/keyboard.h>
 #include <uart8250.h>
 
-extern struct chip_operations superio_via_vt82c686_ops;
-
 struct superio_via_vt82c686_config {
 	struct pc_keyboard keyboard;
 };